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2011-12-12XOP encoding bits and logic.Jan Sjödin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12Also set the proper alignment on inner islands and the function itself.Jakob Stoklund Olesen
Downgrade the alignment of the initial constant island when constant pool entries are moved elsewhere. This is all gated by -arm-align-constant-islands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12Make MF a class member instead of passing it around everywhere.Jakob Stoklund Olesen
Also add an MCP member pointing to the machine constant pool. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146382 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12Add a -arm-align-constant-islands flag, default off.Jakob Stoklund Olesen
Order constant pool entries by descending alignment in the initial island to ensure packing and correct alignment. When the command line flag is set, also align the basic block containing the constant pool entries. This is only a partial implementation of constant island alignment. More to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11Remove some remants of the old palign pattern fragment that were still ↵Craig Topper
hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy
for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11Mips: Don't create a dangling IR function just to get the address of a symbol.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11Also remove unnecessary includes from this file, which was supposed to be partNick Lewycky
of r146334! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10Minimize #include's and forward-declares in Target.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146335 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10Refactor the implementation of the TargetOptions out of TargetMachine, takingNick Lewycky
the only parts of TM that depends on CodeGen headers with it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146334 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10Revert r146322 to appease buildbots. Original commit message:Chad Rosier
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy
for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10Make CR spill and restore use a reserved register. These operations cannot ↵Hal Finkel
use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10Try to align the point where a large basic block is split.Jakob Stoklund Olesen
The split point is picked such that the newly created water has the same alignment as the function. This makes the island suitable for constant pool entries with potentially higher alignment. This also fixes an issue where the basic block was split one instruction too late, causing nonconvergence of the algorithm. <rdar://problem/10550705> There is still an issue with correctly packing differently aligned entries in the island. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10More debug output formatting.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gasRafael Espindola
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC, but it doesn't change the immediate in the same way as when the expression has no right hand side symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09Splats can contain undef's; make sure to handle them correctly. PR11526.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09ARM add some pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146296 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09ARM allows '' syntax, not just '#imm' for assembly.Jim Grosbach
Backwards compatibility with 'gas'. #imm is the preferered and documented syntax, but lots of existing code uses the '$' prefix, so we should support it if we can. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09ARM assembly aliases for BIC<-->AND (immediate).Jim Grosbach
When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09ARM NEON data type aliases for VBIC(register).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach
Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09User a helper overload for a common pattern.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09Tidy up. Better base class factoring.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09Tidy up. Better base class factoring.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09Tweak debugging output.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09This is now implemented.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09X86: Add patterns for the various rounding ops for SSE4.1 and AVX.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09X86: Split (v)rounds[sd] into a normal and an intrinsic version.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146256 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09Move isUnpredicatedTerminator() default implementation to ↵Evan Cheng
TargetInstrInfoImpl to break Target's dependency on CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09Remove hasSSE1orAVX(). It's the same as hasXMM().Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09Rename WrapperPIC. It is now used for both pic and static.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146232 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09jalr should use t9 ($25) for indirect calls regardless of the relocation modelAkira Hatanaka
specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08ARM convenience aliases for VSQRT.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146201 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146196 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter ↵Owen Anderson
can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08ARM VSHR implied destination operand form aliases.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Add various missing AVX patterns which was causing crashes. Sadly, the generatedEvan Cheng
code looks pretty bad compared to SSE. rdar://10538793 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08ARM asm parser, just issue a warning for a duplicate reg in a list.Jim Grosbach
For better 'gas' compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo inAkira Hatanaka
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the target is Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08ARM VSUB implied destination operand form aliases.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There ↵Owen Anderson
don't seem to be patterns for these, so I don't know why they were marked legal in the first place. Fixes failures caused by r146171. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08ARM VQADD implied destination operand form aliases.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08ARM a few more VMUL implied destination operand form aliases.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Implement 64-bit support for thread local storage handling.Akira Hatanaka
- Modify lowering of global TLS address nodes. - Modify isel of ThreadPointer. - Wrap target global TLS address nodes that are operands of loads with WrapperPIC. - Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be substituted with other existing nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson
SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08ARM assembler support for register name aliases.Jim Grosbach
rdar://10550084 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08Many of the SSE patterns should not be selected when AVX is available. This ↵Evan Cheng
led to the following code in X86Subtarget.cpp if (HasAVX) X86SSELevel = NoMMXSSE; This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected. However, this breaks instructions which do not have AVX variants. The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX(). Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change. However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case, the prefetch instructions. rdar://10538297 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146163 91177308-0d34-0410-b5e6-96231b3b80d8
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