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2012-06-29Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.hChandler Carruth
This was always part of the VMCore library out of necessity -- it deals entirely in the IR. The .cpp file in fact was already part of the VMCore library. This is just a mechanical move. I've tried to go through and re-apply the coding standard's preferred header sort, but at 40-ish files, I may have gotten some wrong. Please let me know if so. I'll be committing the corresponding updates to Clang and Polly, and Duncan has DragonEgg. Thanks to Bill and Eric for giving the green light for this bit of cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159421 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
This reverts commit r159406. I noticed a performance regression so I'll back out for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29In the initial exec mode we always do a load to find the address of a variable.Rafael Espindola
Before this patch in pic 32 bit code we would add the global base register and not load from that address. This is a really old bug, but before the introduction of the tls attributes we would never select initial exec for pic code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159409 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick
The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29X86: add more GATHER intrinsics in LLVMManman Ren
Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Changed the formatting sequence of a curly brace to Jack Carter
the comment per code review feedback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159376 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Remove layering violation #include.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159372 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28The Mips specific inline asm operand modifier 'z' has theJack Carter
following description in the gnu sources: Print $0 if operand is zero otherwise print the op normally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27This allows hello world to be compiled for Mips 64 direct object.Jack Carter
It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27This allows hello world to be compiled for Mips 64 direct object.Jack Carter
It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27The ELF relocation record format is different for N64 Jack Carter
which many Mips 64 ABIs use than for O64 which many if not all other target ABIs use. Most architectures have the following 64 bit relocation record format: typedef struct { Elf64_Addr r_offset; /* Address of reference */ Elf64_Xword r_info; /* Symbol index and type of relocation */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset; Elf64_Xword r_info; Elf64_Sxword r_addend; } Elf64_Rela; Whereas N64 has the following format: typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ Elf64_Sxword r_addend; } Elf64_Rela; The structure is the same size, but the r_info data element is now 5 separate elements. Besides the content aspects, endian byte reordering will be different for the area with each element being endianized separately. I treat this as generic and continue to pass r_type as an integer masking and unmasking the byte sized N64 values for N64 mode. I've implemented this and it causes no affect on other current targets. This passes make check. Jack git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27Teach assembler to handle capitalised operation values for DSB instructionsRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27Prevent ARM Assembler crashing on unrecognised assembly format for DSB ↵Richard Barton
instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-27Fix bug in computation of stack size in MipsFrameLowering.cpp.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26Add a missing check to avoid dereference null. No sensible test case ↵Evan Cheng
possible. Sorry. rdar://11745134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159236 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26X86: add GATHER intrinsics (AVX2) in LLVMManman Ren
Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26There are a number of generic inline asm operand modifiers thatJack Carter
up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26Removed unused variableElena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159197 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26Rename to match other X86_64* names.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26Shuffle optimization for AVX/AVX2.Elena Demikhovsky
The current patch optimizes frequently used shuffle patterns and gives these instruction sequence reduction. Before: vshufps $-35, %xmm1, %xmm0, %xmm2 ## xmm2 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm2, %xmm2 ## xmm2 = xmm2[0,2,1,3] vextractf128 $1, %ymm1, %xmm1 vextractf128 $1, %ymm0, %xmm0 vshufps $-35, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm0, %xmm0 ## xmm0 = xmm0[0,2,1,3] vinsertf128 $1, %xmm0, %ymm2, %ymm0 After: vshufps $13, %ymm0, %ymm1, %ymm1 ## ymm1 = ymm1[1,3],ymm0[0,0],ymm1[5,7],ymm0[4,4] vshufps $13, %ymm0, %ymm0, %ymm0 ## ymm0 = ymm0[1,3,0,0,5,7,4,4] vunpcklps %ymm1, %ymm0, %ymm0 ## ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26Remove some duplicate instructions that exist only to given different ↵Craig Topper
mnemonics for the assembler. Use InstAlias instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25Make some ugly hacks for inline asm operands which name a specific register ↵Eli Friedman
a bit more thorough. PR13196. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25ARM: update peephole optimization.Manman Ren
More condition codes are included when deciding whether to remove cmp after a sub instruction. Specifically, we extend from GE|LT|GT|LE to GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we should be able to replace with "sub a, b; movls". rdar: 11725965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25Add SSE2 predicate to CVTPS2PD instructions. Doesn't matter much because ↵Craig Topper
there are no patterns in the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25Remove codegen only instruction in favor of one that has the same ↵Craig Topper
definition. Make some pattern operands more explicit about types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159126 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24%RCX is not a function live-out in eh.return functions.Jakob Stoklund Olesen
The function live-out registers must be live at all function returns, and %RCX is only used by eh.return. When a function also has a normal return, only %RAX holds a return value. This fixes PR13188. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159112 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with ↵Craig Topper
patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with ↵Craig Topper
patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159108 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Fix build failures from r159106.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove intrinsic specific instructions for CVTPD2PS and replace with just ↵Craig Topper
patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159106 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove code i'd been testing with but didn't mean to commit. OopsPete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24DAG legalisation can now handle illegal fma vector types by scalarisationPete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Remove intrinsic specific instructions for (V)CVTDQ2PS. Use a Pat instead ↵Craig Topper
instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional ↵Craig Topper
change because there are no patterns in the instructions. Also fix a typo in a comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to ↵Craig Topper
the SSE2 section of the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Add a microoptimization note.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Extend the IL for selecting TLS models (PR9788)Hans Wennborg
This allows the user/front-end to specify a model that is better than what LLVM would choose by default. For example, a variable might be declared as @x = thread_local(initialexec) global i32 42 if it will not be used in a shared library that is dlopen'ed. If the specified model isn't supported by the target, or if LLVM can make a better choice, a different model may be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Use correct memory types for (V)CVTDQ2PD instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Silence an unused variable warning on release builds.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Compress flags in X86 op folding to reduce space in static tables.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Make helper method static since it doesn't use anything in the class.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with ↵Craig Topper
intrinsic patterns. Mem forms omitted because the load size is only 64-bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159070 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Handle aliases to tls variables in all architectures, not just x86.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159058 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23(sub X, imm) gets canonicalized to (add X, -imm)Evan Cheng
There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach
As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159051 91177308-0d34-0410-b5e6-96231b3b80d8
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