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2012-07-10Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem
multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton
single-precision resiters) (and do it properly this time! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Reverse assembler/disassembler operand order for gather instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10ARM: Allow more flexible patterns in NEON formats.Jim Grosbach
Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Make register Mips::RA allocatable if not in mips16 mode.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Revert r159938 (and r159945) to appease the buildbots.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09X86: implement functions to analyze & synthesize CMOV|SET|JccManman Ren
getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond No functional change intended. If we want to update the condition code of CMOV|SET|Jcc, we first analyze the opcode to get the condition code, then update the condition code, finally synthesize the new opcode form the new condition code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Reapply r158846.Akira Hatanaka
Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Some formatting to keep Clang happyRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Oops - correct broken disassembly for VMOVRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton
single-precision resiters) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Spelling!Richard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09Teach the assembler to use the narrow thumb encodings of various ↵Richard Barton
three-register dp instructions where permissable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07X86: Fix optimizeCompare to correctly check safe condition.Manman Ren
It is safe if EFLAGS is killed or re-defined. When we are done with the basic block, check whether EFLAGS is live-out. Do not optimize away cmp if EFLAGS is live-out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Fix the naming of ensureAlignment. Per the coding standard function namesChad Rosier
should be camel case, and start with a lower case letter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06ARM: Add test cleanup entry to the README.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06revert r159851.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Reapply r158846.Akira Hatanaka
Include file MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06X86: peephole optimization to remove cmp instructionManman Ren
For each Cmp, we check whether there is an earlier Sub which make Cmp redundant. We handle the case where SUB operates on the same source operands as Cmp, including the case where the two source operands are swapped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06Revert r159804, "[arm-fast-isel] Add support for vararg function calls."NAKAMURA Takumi
It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06[arm-fast-isel] Add support for vararg function calls.Jush Lu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159804 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06 Changes per review of commit 159787Jack Carter
Mips specific inline asm operand modifier D. Comment changes and predicate change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05 Mips specific inline asm operand modifier D.Jack Carter
Print the second half of a double word operand. The include list was cleaned up a bit as well. Also the test case was modified to test for both big and little patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-05Enclose instruction rdhwr with directives, which are needed when target isAkira Hatanaka
mips32 rev1 (the directives are emitted when target is mips32r2 too). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Make X86 call and return instructions non-variadic.Jakob Stoklund Olesen
Function argument and return value registers aren't part of the encoding, so they should be implicit operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Ensure CopyToReg nodes are always glued to the call instruction.Jakob Stoklund Olesen
The CopyToReg nodes that set up the argument registers before a call must be glued to the call instruction. Otherwise, the scheduler may emit the physreg copies long before the call, causing long live ranges for the fixed registers. Besides disabling good register allocation, that can also expose problems when EmitInstrWithCustomInserter() splits a basic block during the live range of a physreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Add early if-conversion support to X86.Jakob Stoklund Olesen
Implement the TII hooks needed by EarlyIfConversion to create cmov instructions and estimate their latency. Early if-conversion is still not enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159695 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-03Remove extra space.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-03Change i128mem/i256mem to f128mem/f256mem on some floating point vector ↵Craig Topper
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-03Add aliases for pblendvb, blendvpd, and blendvps instructions with the ↵Craig Topper
implicit xmm0 operand specified. Fixes PR13252. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 mips32 long long register inline asm constraint support.Jack Carter
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Revert " mips32 long long register inline asm constraint support." asEric Christopher
it appears to be breaking the bots. This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159619 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Target option DisableJumpTables is a gross hack. Move it to TargetLowering ↵Evan Cheng
instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 mips32 long long register inline asm constraint support.Jack Carter
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Pass the correct ELFOSABI enumeration to the MipsELFObjectWriter constructorJack Carter
Contributer: Sasa Stankovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Extend TargetPassConfig to allow running only a subset of the normal passes.Bob Wilson
This is still a work in progress but I believe it is currently good enough to fix PR13122 "Need unit test driver for codegen IR passes". For example, you can run llc with -stop-after=loop-reduce to have it dump out the IR after running LSR. Serializing machine-level IR is not yet supported but we have some patches in progress for that. The plan is to serialize the IR to a YAML file, containing separate sections for the LLVM IR, machine-level IR, and whatever other info is needed. Chad suggested that we stash the stop-after pass in the YAML file and use that instead of the start-after option to figure out where to restart the compilation. I think that's a great idea, but since it's not implemented yet I put the -start-after option into this patch for testing purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Consistently use AnalysisID types in TargetPassConfig.Bob Wilson
This makes it possible to just use a zero value to represent "no pass", so the phony NoPassID global variable is no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson
This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Revert accidental checkin.Andrew Trick
My last checkin was apparently not the branch I intended. It was missing one change (added by chandlerc), and contained a spurious change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Do not attempt to use ROR for Thumb1.Bob Wilson
Patch by Matt Fischer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Optimization of shuffle node that can fit to the register form of VBROADCAST ↵Elena Demikhovsky
instruction on AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159504 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Reduce code size by using a second switch statement to avoid extra calls to ↵Craig Topper
SelectAtomic64. Also catch cases where SelectAtomic64 fails. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159503 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Add a break to the end of case statement missed in r159501.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Fix a crash on release builds if gather intrinsics are passed a non-constant ↵Craig Topper
value for the last argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Use a second switch statement to reduce number of calls to SelectGather in ↵Craig Topper
code. Reduces code size a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29ARM: Clean up optimizeCompare in peephole, no functional change.Manman Ren
Use getUniqueVRegDef. Replace a loop with existing interfaces: modifiesRegister and readsRegister. Factor out code into inline functions and simplify the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren
instructions with two register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159465 91177308-0d34-0410-b5e6-96231b3b80d8
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