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2012-07-28X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28Make CVTSS2SI instruction definition consistent with CVTSD2SI.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28Fix up memory load types for SSE scalar convert intrinsic patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160913 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28X86 Peephole: fix PR13475 in optimizeCompare.Manman Ren
It is possible that an instruction can use and update EFLAGS. When checking the safety, we should check the usage of EFLAGS first before declaring it is safe to optimize due to the update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Pass the correct call frame size to callseq_start node. This is needed toAkira Hatanaka
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with the one MachineFrameInfo has. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Remove the X86 sub_ss and sub_sd sub-register indexes completely.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Remove the last mentions of sub_ss and sub_sd from patterns.Jakob Stoklund Olesen
I'll remove these two sub-register indexes shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160831 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Eliminate sub_ss, sub_sd from broadcast patterns.Jakob Stoklund Olesen
The (COPY_TO_REGCLASS GR32:$src, VR128) pattern looks odd, but copyPhysReg does the right thing with it. (The old pattern would eventually produce the same cross-class copy). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Eliminate more sub_ss / sub_sd patterns.Jakob Stoklund Olesen
This gets rid of some more INSERT_SUBREG - IMPLICIT_DEF patterns, simplifying the emitted code a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Eliminate some SUBREG_TO_REG patterns with sub_ss and sub_sd.Jakob Stoklund Olesen
The SUBREG_TO_REG instruction has magic semantics asserting that the source value was defined by an instruction that cleared the high half of the register. Those semantics are never actually exploited for xmm registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Eliminate a batch of uses of sub_ss and sub_sd in the X86 target.Jakob Stoklund Olesen
These idempotent sub-register indices don't do anything --- They simply map XMM registers to themselves. They no longer affect register classes either since the SubRegClasses field has been removed from Target.td. This patch replaces XMM->XMM EXTRACT_SUBREG and INSERT_SUBREG patterns with COPY_TO_REGCLASS patterns which simply become COPY instructions. The number of IMPLICIT_DEF instructions before register allocation is reduced, and that is the cause of the test case changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Make l/q suffixes on AVX forms of scalar convert instructions consistent ↵Craig Topper
with their non-AVX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Fix call setup for PIC.Akira Hatanaka
Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25ARM: Don't assume an SDNode is a constant.Jim Grosbach
Before accessing a node as a ConstandSDNode, make sure it actually is one. No testcase of non-trivial size. rdar://11948669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25make all Emit*() functions consult the TargetLibraryInfo information before ↵Nuno Lopes
creating a call to a library function. Update all clients to pass the TLI information around. Previous draft reviewed by Eli. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25Fix typos. Thanks to Matt Beaumont-Gay for noticing it.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160731 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25When a return struct pointer is passed in registers, the called has nothingRafael Espindola
to pop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25Factor a long list of conditions into a predicate function. No functionalityRafael Espindola
change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25Eliminate the stack slot used to save the global base register.Akira Hatanaka
The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24Fix a bug in the x86 disassembler's symbolic disassembly support for Jcc-JumpKevin Enderby
if Condition Is Met instuctions that was not correctly determining the target instruction. So for a jne rel32 instruction: % cat x.s .byte 0x0f, 0x85, 0x09, 0x00, 0x00, 0x00 % as x.s it was incorrectly deterining the target: % otool -q -tv a.out a.out: (__TEXT,__text) section 0000000000000000 jne 0xd and with the fix it gets this correct as: % otool -q -tv a.out a.out: (__TEXT,__text) section 0000000000000000 jne 0xf rdar://11505997 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24add a few more functions to TargetLibraryInfo:Nuno Lopes
fputc, memchr, memcmp, putchar, puts, strchr, strncmp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160690 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24ELF does not imply GNU/Linux. Do not assume GNU conventions just because weDavid Chisnall
are targeting an ELF platform. Only fold gs-relative (and fs-relative) loads if it is actually sensible to do so for the target platform. This fixes PR13438. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24TargetLibraryInfo: add strn?cat, strn?cpy, and strn?lenNuno Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160678 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24Fix function MipsCodeEmitter::emitExternalSymbolAddress to pass testAkira Hatanaka
ExecutionEngine/test-fp.ll. Patch by Petar Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23Add basic ability to setup call frame, and make procedure calls.Akira Hatanaka
Hello world will compile and execute with this patch. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23Add comment for relocations MO_HIGHER and HIGHEST in MipsBaseInfo.h.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160636 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23Test revert of test changes.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23Test commit.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23Fix a typo (the the => the)Sylvestre Ledru
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-21Fix Mips long branch pass.Akira Hatanaka
This pass no longer requires that the global pointer value be saved to the stack or register since it uses bal instruction to compute branch distance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-21Add HIGHER and HIGHEST relocations to Mips backend.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-21Revert accidental commit.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160598 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-21Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.Akira Hatanaka
Test case will be added later when long branch patch is checked in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160597 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-20Don't use implicit register operands to calculate L-bit for AVX ↵Craig Topper
instructions. Needed because super reg defs and kills are added as implicit operands on 128-bit instructions. Fixes PR13349. Patch by Jose Fonseca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Adds the family codes for the Midview Atom processors so that thePreston Gurd
Atom buildbot will auto-detect Atom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19default to use -mv4 when no version of Hexagon has been specifiedSebastian Pop
This fixes a bunch of make check failures of the form: Unknown Architecture Version. UNREACHABLE executed at ../lib/Target/Hexagon/HexagonSubtarget.cpp:60! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19[arm-fast-isel] Add support for vararg function calls.Jush Lu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Remove tabs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160483 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Remove tabs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160479 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Remove tabs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Remove tabs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160476 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18X86: remove redundant cmp against zero.Manman Ren
Updated OptimizeCompare in peephole to remove redundant cmp against zero. We only remove Compare if CF and OF are not used. rdar://11855129 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18This patch fixes 8 out of 20 unexpected failures in "make check"Preston Gurd
when run on an Intel Atom processor. The failures have arisen due to changes elsewhere in the trunk over the past 8 weeks or so. These failures were not detected by the Atom buildbot because the CPU on the Atom buildbot was not being detected as an Atom CPU. The fix for this problem is in Host.cpp and X86Subtarget.cpp, but shall remain commented out until the current set of Atom test failures are fixed. Patch by Andy Zhang and Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.Andrew Trick
Based on Evan's suggestion without a commitable test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160441 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160440 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18The vbroadcast family of instructions has 'fallback patterns' in case where theNadav Rotem
load source operand is used by multiple nodes. The v2i64 broadcast was emulated by shuffling the two lower i32 elements to the upper two. We had a bug in the immediate used for the broadcast. Replacing 0 to 0x44. 0x44 means [01|00|01|00] which corresponds to the correct lane. Patch by Michael Kuperstein. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160430 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Mips specific inline asm operand modifier 'M':Jack Carter
Print the high order register of a double word register operand. In 32 bit mode, a 64 bit double word integer will be represented by 2 32 bit registers. This modifier causes the high order register to be used in the asm expression. It is useful if you are using doubles in assembler and continue to control register to variable relationships. This patch also fixes a related bug in a previous patch: case 'D': // Second part of a double word register operand case 'L': // Low order register of a double word register operand case 'M': // High order register of a double word register operand I got 'D' and 'M' confused. The second part of a double word operand will only match 'M' for one of the endianesses. I had 'L' and 'D' be the opposite twins when 'L' and 'M' are. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Remove tab characters.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Fix typo in error message and remove some tab characters.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160423 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper
instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
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