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2012-09-13Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper
byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13Don't fold indexed loads into TCRETURNmi64.Jakob Stoklund Olesen
We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Misc.Akira Hatanaka
1. Remove RA from list of allocatable registers 2. Enable d,y,r constraint inline assembly instructions Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Fix PR11985Michael Liao
- BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12[ms-inline asm] Make the operand size directives case insensitive.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Enable exceptions handling on PPC64 now that cr misaligned spillingRoman Divacky
was fixed in r163713. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163715 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12This patch corrects logic in PPCFrameLowering for save and restore of ↵Roman Divacky
nonvolatile condition register fields across calls under the SVR4 ABIs. * With the 64-bit ABI, the save location is at a fixed offset of 8 from the stack pointer. The frame pointer cannot be used to access this portion of the stack frame since the distance from the frame pointer may change with alloca calls. * With the 32-bit ABI, the save location is just below the general register save area, and is accessed via the frame pointer like the rest of the save areas. This is an optional slot, so it must only be created if any of CR2, CR3, and CR4 were modified. * For both ABIs, save/restore logic is generated only if one of the nonvolatile CR fields were modified. I also took this opportunity to clean up an extra FIXME in PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless for the 64-bit ABI, so I removed them for correctness and efficiency. Fixes PR13708 and partially also PR13623. It lets us enable exception handling on PPC64. Patch by William J. Schmidt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163713 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Add support for AMD Geode.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163710 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Indentation fixes. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163682 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Rename the isMemory() function to isMem(). No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Release build: guard dump functions withManman Ren
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11StringSwitchify.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Simplify logic. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163648 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen
Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Make a bunch of lowering helper functions static instead of member ↵Craig Topper
functions. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163596 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper
table size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163594 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick
The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Update function names to conform to guidelines. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Revert r163556. Missed updates to tablegen files.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Update function names to conform to guidelines. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Remove redundant semicolons which are null statements.Dmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10[ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() functionChad Rosier
and update the printOperand() function accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10[ms-inline asm] Add support for .att_syntax directive.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen
The ARM backend can eliminate cmp instructions by reusing flags from a nearby sub instruction with similar arguments. Don't do that if the sub is predicated - the flags are not written unconditionally. <rdar://problem/12263428> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163535 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Enhance PR11334 fix to support extload from v2f32/v4f32Michael Liao
- Fix an remaining issue of PR11674 as well git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Add "blocked" heuristic to the Hexagon MI scheduler.Sergei Larin
Improve AQ instruction selection in the Hexagon MI scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Add boolean simplification support from CMOVMichael Liao
- If a boolean value is generated from CMOV and tested as boolean value, simplify the use of test result by referencing the original condition. RDRAND intrinisc is one of such cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163516 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10The VPSHUFB 256-bit instruction may be generated when one of input vector is ↵Elena Demikhovsky
undefined or zeroinitializer. I've added the "zeroinitializer" case in this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163506 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Make helper function static.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163504 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-09Add missing space before {. No functionality change.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163484 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163473 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08Use 256-bit alignment for constant pool value for 256-bit vector FNEG lowering.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163463 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08Add support for lowering FABS of vector types.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper
FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer
For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen
The 'select' transformations apply to all ARM architectures and don't require hasV6T2Ops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07MC: Overhaul handling of .lcommBenjamin Kramer
- Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer
registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163390 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07MipsAsmParser: Fix a couple of string use-after-frees and misuses of classof.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163383 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07The Mips standalone assembler aliased instruction support.Jack Carter
The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07The Mips standalone assembler intial directive support.Jack Carter
Actually these are just stubs for parsing the directives. Semantic support will come later. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07The Mips standalone assembler fpu instruction support.Jack Carter
Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Remove unused variable introduced by r163346.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163359 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06The Mips standalone assembler memory instruction support.Jack Carter
This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw Test case included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Release build: guard dump functions with "ifndef NDEBUG"Manman Ren
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover
Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover
instructions. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Use correct part of complex operand to encode VST1 alignment.Tim Northover
Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06AVX2 optimization.Elena Demikhovsky
Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163312 91177308-0d34-0410-b5e6-96231b3b80d8
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