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2012-10-26[ms-inline asm] Add a comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-2680 col.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Remove ARMBaseRegisterInfo::isReservedReg().Jakob Stoklund Olesen
It is just as easy to use MRI::isReserved() now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Add GPRPair Register class to ARM.Jakob Stoklund Olesen
Some instructions in ARM require 2 even-odd paired GPRs. This patch adds support for such register class. Patch by Weiming Zhao! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Remove the canCombineSubRegIndices() target hook.Jakob Stoklund Olesen
The new coalescer can already do all of this, so there is no need to duplicate the efforts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Emit an error for unsupported SIZE and LENGTH directives.Chad Rosier
Part of rdar://12576868 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Add support for the TYPE operator.Chad Rosier
Part of rdar://12576868 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166790 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166780 ↵Reed Kotler
91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Have the target AsmParser create the asmrewrite for the offsetofChad Rosier
operator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Better handling of OpcodeToISD using enum/switch.Renato Golin
Patch by Pasi Parviainen <pasi.parviainen@iki.fi> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26PowerPC: Fix for rldcl/rldicl/rldicr MC emissionAdhemerval Zanella
This patch fixes the rldcl/rldicl/rldicr instruction emission. The issue is the MDForm_1 instruction defines the PowerISA MB field from 'rldicl' with the name MBE, but RLDCL/RLDICL/RLDICR definition uses as 'MB'. It end up by generatint the 'rldicl' enconding at 'lib/Target/PowerPC/PPCGenMCCodeEmitter.inc' to use the fourth argument as the third. The patch changes it by adjusting to use the fourth argument as intended. Fixes PR14180. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Fix CPP backend for method attributes by creating a block where a new ↵Nicolas Geoffray
AttrBuilder is defined for each attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Implement carry for subtract/add for mips16Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Add VectorTargetTransform::getNumberOfParts.Hal Finkel
As discussed on IRC, add VectorTargetTransform::getNumberOfParts to provide a stable interface to the vector legalization splitting factor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26implement large (>16 bit) constant loading.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25[ms-inline asm] Perform field lookups with the dot operator.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25implement mips16 patterns for select nodesReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25[ms-inline asm] Add support for creating AsmRewrites in the target specificChad Rosier
AsmParser logic. To be used/tested in a subsequent commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Minor cleanups.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25[ms-inline asm] Add error handling to the ParseIntelDotOperator() function.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25This patch fixes the MC object emission of 'nop' for external function callsAdhemerval Zanella
and also fixes the R_PPC64_TOC16 and R_PPC64_TOC16_DS relocation offset. The 'nop' is needed so a restore TOC instruction (ld r2,40(r1)) can be placed by the linker to correct restore the TOC of previous function. Current code has two issues: it defines in PPCInstr64Bit.td file a LDinto_toc and LDtoc_restore as a DSForm_1 with DS_RA=0 where it should be DS=2 (the 8 bytes displacement of the TOC saving). It also wrongly emits a MC intruction using an uint32_t value while the PPC::BL8_NOP_ELF and PPC::BLA8_NOP_ELF are both uint64_t (because of the following 'nop'). This patch corrects the remaining ExecutionEngine using MCJIT: ExecutionEngine/2002-12-16-ArgTest.ll ExecutionEngine/2003-05-07-ArgumentTest.ll ExecutionEngine/2005-12-02-TailCallBug.ll ExecutionEngine/hello.ll ExecutionEngine/hello2.ll ExecutionEngine/test-call.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166682 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25This patch addresses a PPC64 ELF issue with passing parameters consisting ofBill Schmidt
structs having size 3, 5, 6, or 7. Such a struct must be passed and received as right-justified within its register or memory slot. The problem is only present for structs that are passed in registers. Previously, as part of a patch handling all structs of size less than 8, I added logic to rotate the incoming register so that the struct was left- justified prior to storing the whole register. This was incorrect because the address of the parameter had already been adjusted earlier to point to the right-adjusted value in the storage slot. Essentially I had accidentally accounted for the right-adjustment twice. In this patch, I removed the incorrect logic and reorganized the code to make the flow clearer. The removal of the rotates changes the expected code generation, so test case structsinregs.ll has been modified to reflect this. I also added a new test case, jaggedstructs.ll, to demonstrate that structs of these sizes can now be properly received and passed. I've built and tested the code on powerpc64-unknown-linux-gnu with no new regressions. I also ran the GCC compatibility test suite and verified that earlier problems with these structs are now resolved, with no new regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Initial TOC support for PowerPC64 object creationAdhemerval Zanella
This patch adds initial PPC64 TOC MC object creation using the small mcmodel (a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC, R_PPC64_TOC16, and R_PPC64_TOC16DS). The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter' is meant to avoid the creation of an unreferenced ".TOC." symbol (used in the .odp creation) as well to set the R_PPC64_TOC relocation target as the temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should not point to any symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166677 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Atom has SIMD instruction set extension up to SSSE3Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Clean up where SlotSize should be used instead of pointer size.Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Implement a basic cost model for vector and scalar instructions. Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166642 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24[ms-inline asm] Add support for parsing the '.' operator. Given,Chad Rosier
[register].field The operator returns the value at the location pointed to by register plus the offset of field within its structure or union. This patch only handles immediate fields (i.e., [eax].4). The original displacement has to be a MCConstantExpr as well. Part of rdar://12470415 and rdar://12470514 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Tidy up. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Fix a miscompilation caused by a typo. When turning a adde with negative valueEvan Cheng
into a sbc with a positive number, the immediate should be complemented, not negated. Also added a missing pattern for ARM codegen. rdar://12559385 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166613 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Add some cleanup to the DataLayout changes requested by Chandler.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Implement a basic VectorTargetTransformInfo interface to be used by the loop ↵Nadav Rotem
and bb vectorizers for modeling the cost of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24[ms-inline asm] Create a register operand, rather than a memory operand when weChad Rosier
see the offsetof operator. Previously, we were matching something like MOVrm in the front-end and later matching MOVrr in the back-end. This change makes things more consistent. It also fixes cases where we can't match against a memory operand as the source (test cases coming). Part of rdar://12470317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Add in support for getIntPtrType to get the pointer type based on the ↵Micah Villmow
address space. This checkin also adds in some tests that utilize these paths and updates some of the clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Special calling conventions for Intel OpenCL built-in library.Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Add custom conversion from v2u32 to v2f32 in 32-bit modeMichael Liao
- As there's no 64-bit GPRs in 32-bit mode, a custom conversion from v2u32 to v2f32 is added to improve the efficiency of the code generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24[mips] Make sure sret argument is returned in register V0.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166539 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Change x86_fastcallcc to require inreg markers. This allows it to knownRafael Espindola
the difference from "int x" (which should go in registers and "struct y {int x;}" (which should not). Clang will be updated in the next patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23[ms-inline asm] Offset operator - the size should be based on the size of aChad Rosier
pointer, not the size of the variable. Part of rdar://12470317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23[ms-inline asm] Clean up comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23[ms-inline asm] When parsing inline assembly we set the base register to aChad Rosier
non-zero value as we don't know the actual value at this point. This is necessary to get the matching correct in some cases. However, the actual value set as the base register doesn't matter, since we're just matching not emitting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Make branch heavy code for generating marked up disassembly simplerKevin Enderby
and easier to read by adding a couple helper functions. Suggestion by Chandler Carruth and seconded by Meador Inge! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166515 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Fix PR14161Michael Liao
- Check index being extracted to be constant 0 before simplfiying. Otherwise, retain the original sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166504 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Silence -Wsign-compareMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23[ms-inline asm] Add an implementation of the offset operator. This is a followChad Rosier
on patch to r166433. rdar://12470317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166488 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Add custom UINT_TO_FP from v4i8/v4i16/v8i8/v8i16 to v4f32/v8f32Michael Liao
- Replace v4i8/v8i8 -> v8f32 DAG combine with custom lowering to reduce DAG combine overhead. - Extend the support to v4i16/v8i16 as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Enable lowering ZERO_EXTEND/ANY_EXTEND to PMOVZX from SSE4.1Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23This is another TLC patch for separating code for the Darwin and ELF ABIsBill Schmidt
for the PowerPC target, and factoring the results. This will ease future maintenance of both subtargets. PPCTargetLowering::LowerCall_Darwin_Or_64SVR4() has grown a lot of special-case code for the different ABIs, making maintenance difficult. This is getting worse as we repair errors in the 64-bit ELF ABI implementation, while avoiding changes to the Darwin ABI logic. This patch splits the routine into LowerCall_Darwin() and LowerCall_64SVR4(), allowing both versions to be significantly simplified. I've factored out chunks of similar code where it made sense to do so. I also performed similar factoring on LowerFormalArguments_Darwin() and LowerFormalArguments_64SVR4(). There are no functional changes in this patch, and therefore no new test cases have been developed. Built and tested on powerpc64-unknown-linux-gnu with no new regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166480 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23implement setXX patternsReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22When a block ends in an indirect branch, add its successors to the machine ↵Bill Wendling
basic block. The CFG of the machine function needs to know that the targets of the indirect branch are successors to the indirect branch. <rdar://problem/12529625> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166448 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22Add support for annotated disassembly output for X86 and arm.Kevin Enderby
Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8
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