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2013-01-18Calculate vector element size more directly for VINSERTF128/VEXTRACTF128 ↵Craig Topper
immediate handling. Also use MVT since this only called on legal types during pattern matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18Minor formatting fix. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172795 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18Spelling fix: extened->extended. Trailing whitespace in same function.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172793 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18Make more use of is128BitVector/is256BitVector in place of getSizeInBits() ↵Craig Topper
== 128/256. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18[ms-inline asm] Make the error message more generic now that we support the Chad Rosier
'SIZE' and 'LENGTH' operators. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17This patch fixes PR13626 by providing i128 support in the returnBill Schmidt
calling convention. 128-bit integers are now properly returned in GPR3 and GPR4 on PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172745 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17[ms-inline asm] Add support for the 'SIZE' and 'LENGTH' operators.Chad Rosier
Part of rdar://12576868 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172743 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Add indexed load/store instructions for offset validation check.Jyotsna Verma
This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17This patch fixes the PPC calling convention to handle returns ofBill Schmidt
_Complex float and _Complex long double, by simply increasing the number of floating point registers available for return values. The test case verifies that the correct registers are loaded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Optimization for the following SIGN_EXTEND pairs:Elena Demikhovsky
v8i8 -> v8i64, v8i8 -> v8i32, v4i8 -> v4i64, v4i16 -> v4i64 for AVX and AVX2. Bug 14865. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so ↵Craig Topper
they get instantiated together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172704 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Provide a place for targets to insert ILP optimization passes.Jakob Stoklund Olesen
Move the early if-conversion pass into this group. ILP optimizations usually need to find the right balance between register pressure and ILP using the MachineTraceMetrics analysis to identify critical paths and estimate other costs. Such passes should run together so they can share dominator tree and loop info analyses. Besides if-conversion, future passes to run here here could include expression height reduction and ARM's MLxExpansion pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17This is a resubmittal. For some reason it broke the bots yesterdayJack Carter
but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Change CostTable model to be global to all targetsRenato Golin
Moving the X86CostTable to a common place, so that other back-ends can share the code. Also simplifying it a bit and commoning up tables with one and two types on operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172658 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16reverting 172579Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Akira,Jack Carter
Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-15This patch fixes a Mips specific bug where Jack Carter
we need to generate a N64 compound relocation R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE. The bug was exposed by the SingleSourcetest case DuffsDevice.c. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14[ms-inline asm] Extend support for parsing Intel bracketed memory operands thatChad Rosier
have an arbitrary ordering of the base register, index register and displacement. rdar://12527141 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Improve r172468: const_cast is not needed hereDmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172483 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Improve r172471: avoid all those extra casts on the lines nearbyDmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172481 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Follow up of commit r172472.Quentin Colombet
Refactor the big if/else sequence into one string switch for ARM subtype selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172475 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Complete the existing support of ARM v6m, v7m, and v7em, i.e., respectively ↵Quentin Colombet
cortex-m0, cortex-m3, and cortex-m4 on the backend side. Adds new subtype values for the MachO format and use them when the related triple are set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Fix CastingDavid Greene
Fix a casting-away-const compiler warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Fix Another CastDavid Greene
Properly cast code to eliminate cast-away-const errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172468 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Simplify nested strconcats in X86 td files since strconcat can take more ↵Craig Topper
than 2 arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172379 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents ↵Craig Topper
needing to specify everything twice. No functional change intended git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172378 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13Fix typo in comment.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13Remove redundant 'llvm::' qualificationsDmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13X86: Add patterns for X86ISD::VSEXT in registers.Benjamin Kramer
Those can occur when something between the sextload and the store is on the same chain and blocks isel. Fixes PR14887. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a ↵NAKAMURA Takumi
warning. [-Wunused-function] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172319 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12MipsAsmParser: Try to unbreak tests to add extra check.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12This patch tackles the problem of parsing Mips Jack Carter
register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11Update patch for the pad short functions pass for Intel Atom (only).Preston Gurd
Adds a check for -Oz, changes the code to not re-visit BBs, and skips over DBG_VALUE instrs. Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11X86AsmParser.cpp: Fix up r172148, to add initializer in another CreateMem().NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10Remove heavy and unused #inclues from X86TargetObjectFile.cpp.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10[ms-inline asm] Make sure we set a default value for AddressOf. Follow on toChad Rosier
r172121. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10[ms-inline asm] Add support for calling functions from inline assembly.Chad Rosier
Part of rdar://12991541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09Fix description of ARMOperandJoel Jones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09ARM Cost model: Use the size of vector registers and widest vectorizable ↵Nadav Rotem
instruction to determine the max vectorization factor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09PowerPC: EH adjustmentsAdhemerval Zanella
This patch adjust the r171506 to make all DWARF enconding pc-relative for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT (since the eh_frame will not generate PIC-relative relocation) and also adds the emission of stubs created by the TTypeEncoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171979 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09Efficient lowering of vector sdiv when the divisor is a splatted power of ↵Nadav Rotem
two constant. PR 14848. The lowered sequence is based on the existing sequence the target-independent DAG Combiner creates for the scalar case. Patch by Zvi Rackover. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09Last in the series of removing unnecessary '0' arguments forEric Christopher
address space. Reordered the EmitULEB128IntValue arguments to make this easier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171949 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09MIsched: add an ILP window property to machine model.Andrew Trick
This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09These functions have default arguments of 0 for the last arg. UseEric Christopher
them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171933 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09Cost Model: Move the 'max unroll factor' variable to the TTI and add initial ↵Nadav Rotem
Cost Model support on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08This patch produces the correct addend value forJack Carter
an R_MIPS_GPREL16 relocation. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08This patch produces the correct pointer size Jack Carter
value in the 64 bit .eh_frame section. It doesn't however allow exception handling to work yet since it depends on the correct relocation model being set in the ELF header flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08Pad Short Functions for Intel AtomPreston Gurd
The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. This patch has been updated to address Nadav's review comments - Optimize only at >= O1 and don't do optimization if -Os is set - Stores MachineBasicBlock* instead of BBNum - Uses DenseMap instead of std::map - Fixes placement of braces Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171879 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-08Renamed MCInstFragment to MCRelaxableFragment and added some comments.Eli Bendersky
No change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-07ARM: Copy-paste error.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171790 91177308-0d34-0410-b5e6-96231b3b80d8
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