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2013-01-30[mips] Lower EH_RETURN.Akira Hatanaka
Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173862 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Adding simple cast cost to ARMRenato Golin
Changing ARMBaseTargetMachine to return ARMTargetLowering intead of the generic one (similar to x86 code). Tests showing which instructions were added to cast when necessary or cost zero when not. Downcast to 16 bits are not lowered in NEON, so costs are not there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173849 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Use multiclass for post-increment store instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Add constant extender support for MInst type instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173813 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Remove dead code.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173812 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29R600/AMDILPeepholeOptimizer.cpp: Tweak std::make_pair to satisfy C++11.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Fix typo in X86BaseInfo.h that I introduced in r157818.Hans Wennborg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Fix 64-bit atomic operations in Thumb mode.Tim Northover
The ARM and Thumb variants of LDREXD and STREXD have different constraints and take different operands. Previously the code expanding atomic operations didn't take this into account and asserted in Thumb mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng
conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Add isBGQ method to PPCSubtargetHal Finkel
This function will be used in future commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173729 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Fix 256-bit PALIGNR comment decoding to understand that it works on ↵Craig Topper
independent 256-bit lanes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Add missing break in 256-bit palignr comment printing. No test case yet ↵Craig Topper
because the comment itself is still wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173669 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Fix inconsistent usage of PALIGN and PALIGNR when referring to the same ↵Craig Topper
instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Remove addToNoHelperNeeded function that was left unused after r173649. ↵Craig Topper
Fixes a -Wunused warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173664 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Make some code a little simpler.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173649 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2rus instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 1r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 0r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27Convert the CPP backend to use the AttributeSet instead of AttributeWithIndex.Bill Wendling
Further removal of the introspective AttributeWithIndex thing. Also fix the #includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173599 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26X86: Do splat promotion later, so the optimizer can chew on it first.Benjamin Kramer
This catches many cases where we can emit a more efficient shuffle for a specific mask or when the mask contains undefs. Once the splat is lowered to unpacks we can't do that anymore. There is a possibility of moving the promotion after pshufb matching, but I'm not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so I avoided that for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26fix use of std::std. it's ordered set.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173563 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Remove unused variables, silences -Wunused-variableDmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Remove some introspection functions.Bill Wendling
The 'getSlot' function and its ilk allow introspection into the AttributeSet class. However, that class should be opaque. Allow access through accessor methods instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173522 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Initial implementation of PPCTargetTransformInfoHal Finkel
This provides a place to add customized operation cost information and control some other target-specific IR-level transformations. The only non-trivial logic in this checkin assigns a higher cost to unaligned loads and stores (covered by the included test case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky
(defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l4r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Use the new 'getSlotIndex' method to retrieve the attribute's slot index.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Use the correct format in the STW / SETPSC instruction names.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Fix order of operands for crc8_l4rRichard Osborne
The order in which operands appear in the encoded instruction is different to order in which they appear in assembly. This changes the XCore backend to use the instruction encoding order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l5r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Fix order of operands for l5r instructions.Richard Osborne
With this change the operands order matches the order in which the operands are encoded in the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Use correct mnemonic / instruction name for ldivu.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25More cleanup of PPC register definitions.Hal Finkel
Uses the new !add TableGen operator to do more cleanup of the PPC register definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Fixed the condition codes for the atomic64 min/umin code generation on ARM. ↵Silviu Baranga
If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173437 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick
Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25This patch implements parsing the .wordJack Carter
directive for the Mips assembler. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25[mips] Set flag neverHasSideEffects flag on some of the floating point ↵Akira Hatanaka
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24Moving Cost Tables up to share with other targetsRenato Golin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24Start cleanup of PPC register definitions using foreach loops.Hal Finkel
No functionality change intended. This captures the first two cases GPR32/64. For the others, we need an addition operator (if we have one, I've not yet found it). Based on a suggestion made by Tom Stellard in the AArch64 review! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24MipsISelLowering.cpp: Fill unreachable paths to fix warnings. ↵NAKAMURA Takumi
[-Wsometimes-uninitialized] FIXME: Could they, unreachable(s), be removed? FIXME: I could prefer the coding standards... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173325 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24MipsISelLowering.cpp: Fix a warning, take two. [-Wunused-variable]NAKAMURA Takumi
...and fix a typo, s/#ifdef/#ifndef/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24MipsISelLowering.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173323 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24The next phase of Mips16 hard float implementation.Reed Kotler
Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173320 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23R600: Add a llvm.R600.store.swizzle intrinsicsTom Stellard
This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its name. It is used to store vs/fs outputs Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23R600: Simplify stream outputs intrinsicTom Stellard
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173296 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Add instruction encodings / disassembly support for l6r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Fix powerpc test failure - forgot to initialize stack slot size for ↵Eli Bendersky
PPCLinuxMCAsmInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173275 91177308-0d34-0410-b5e6-96231b3b80d8
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