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2013-02-07[mips] Make Filler a class and reduce indentation.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174666 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Constrain PowerPC autovectorization to fix bug 15041.Bill Schmidt
Certain vector operations don't vectorize well with the current PowerPC implementation. Element insert/extract performs poorly without VSX support because Altivec requires going through memory. SREM, UREM, and VSELECT all produce bad scalar code. There's a lot of work to do for the cost model before autovectorization will be tuned well, and this is not an attempt to address the larger problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174660 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07[mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka
Change the original JALR instruction with one register operand to be a pseudo-instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: cleanup VGPR encodingTom Stellard
Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Handle VGPR64 destination in copyPhysReg().Tom Stellard
Allows nexuiz to run with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174655 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Add pattern for mul.Tom Stellard
20 more little piglits with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174654 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: simplify and fix SMRD encodingTom Stellard
The _SGPR variants where wrong. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174653 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: add proper 64bit immediate support v2Tom Stellard
v2: rebased on current upstream Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174652 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Add an explicit default processorTom Stellard
This is for the case when no processor is passed to the backend. This prevents the '' is not a recognized processor for this target (ignoring processor) warning from being generated by clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174651 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Use proper instructions for array/shadow samplers.Tom Stellard
Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Make sample intrinsic address parameter type overloaded.Tom Stellard
Handle vectors of 1 to 16 integers. Change the intrinsic names to prevent the wrong one from being selected at runtime due to the overloading. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Add basic support for more integer vector types.Tom Stellard
v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07ARM cost model: Add costs for vector selectsArnold Schwaighofer
Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600/SI: Add pattern for flog2Michel Danzer
22 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174615 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Consolidate sub register indices.Tom Stellard
Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Add support for SET*_DX10 instructionsTom Stellard
These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174609 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07R600: Fix assembly name for SETGT_INTTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174607 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Make sure we call externals from libraries properly when -static.Reed Kotler
For example, when we are doing mips16 hard float or soft float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174583 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Enable jumps when in -static mode.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06[mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0".Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06This is a follow-up on r174446, now taking Atom processors intoEli Bendersky
account. Atoms use LEA for updating SP in prologs/epilogs, and the exact LEA opcode depends on the data model. Also reapplying the test case which was added and then reverted (because of Atom failures), this time specifying explicitly the CPU in addition to the triple. The test case now checks all variations (data mode, cpu Atom vs. Core). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174542 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06PPC calling convention cleanup.Bill Schmidt
Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI. Rename things to clarify this. Also delete some code that's been commented out for a long time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06R600: Support for indirect addressing v4Tom Stellard
Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Implement external weak (ELF) symbols on AArch64Tim Northover
Weakly defined symbols should evaluate to 0 if they're undefined at link-time. This is impossible to do with the usual address generation patterns, so we should use a literal pool entry to materlialise the address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add AArch64 CRC32 instructionsTim Northover
These instructions are a late addition to the architecture, and may yet end up behind an optional attribute, but for now they're available at all times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add icache prefetch operations to AArch64Tim Northover
This adds hints to the various "prfm" instructions so that they can affect the instruction cache as well as the data cache. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06ARM: Use MCTargetAsmParser::validateTargetOperandClass().Jim Grosbach
Use the validateTargetOperandClass() hook to match literal '#0' operands in InstAlias definitions. Previously this required per-instruction C++ munging of the operand list, but not is handled as a natural part of the matcher. Much better. No additional tests are required, as the pre-existing tests for these instructions exercise the new behaviour as being functionally equivalent to the old. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174488 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Make sure the correct opcodes are used to SUB and ADD the stackEli Bendersky
pointer in function prologs/epilogs. The opcodes should depend on the data model (LP64 vs. ILP32) rather than the architecture bit-ness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05[mips] Do not use function CC_MipsN_VarArg unless the function being analyzedAkira Hatanaka
is a vararg function. The original code was examining flag OutputArg::IsFixed to determine whether CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this flag is often set to false when the function being analyzed is a non-variadic function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to AArch64 return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174415 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to XCore return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174414 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to Sparc return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to MSP430 return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174411 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to Mips return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to PowerPC return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to MBlaze return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to Hexagon return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to ARM return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to X86 return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Don't use MRI liveouts in R600.Jakob Stoklund Olesen
Something very strange is going on with the output registers in this target. Its ISelLowering code is inserting dangling CopyToReg nodes, hoping that those physregs won't get clobbered before the RETURN. This patch adds the output registers as implicit uses on RETURN instructions in the custom emission pass. I'd much prefer to have those CopyToReg nodes glued to the RETURNs, but I don't see how. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Avoid using MRI::liveout_iterator for computing VRSAVEs.Jakob Stoklund Olesen
The liveout lists are about to be removed from MRI, this is the only place they were used after register allocation. Get the live out V registers directly from the return instructions instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05R600: Fold remaining CONST_COPY after expand pseudo instTom Stellard
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174395 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05R600: improve inputs/interpolation handlingTom Stellard
Use one intrinsic for all sorts of interpolation. Use two separate unexpanded instructions to represent INTERP_XY and _ZW - this will allow to eliminate one part if it's not used. Track liveness of special interpolation regs instead of reserving them - this will allow to reuse those regs, lowering reg pressure. Patch By: Vadim Girlin v2[Vincent Lejeune]: Rebased against current llvm master Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05R600: Emit function name in the AsmPrinterTom Stellard
Emitting the function name allows us to check for it in the FileCheck tests so we can make sure FileCheck is checking the output of the correct function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05R600/SI: Add patterns for fcos and fsin.Tom Stellard
Fixes 37 piglit tests and allows e.g. FlightGear to run with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Fix commentsEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma
for the existing instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Fix signed-unsigned comparison warning.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174387 91177308-0d34-0410-b5e6-96231b3b80d8
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