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2010-10-28Reduce malloc thrashing.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28rearrange ParseRegisterList.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28refactor some code to simplify it, eliminating some owningptr's.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng
to fail. Ugh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28- Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng
- For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Fix pastos in handling of AVX cvttsd2si, PR8491.Dale Johannesen
Bruno, please review, but I'm pretty sure this is right. Patch by Alex Mac! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Add correct NEON encodings for vtbl and vtbx.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Add correct NEON encodings for vext, vtrn, vuzp, and vzip.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Fix compiler warnings about signed/unsigned comparisons.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Shifter ops are not always free. Do not fold them (especially to formEvan Cheng
complex load / store addressing mode) when they have higher cost and when they have more than one use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach
the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson
encoding for specifying fractional bits for fixed point conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Provide correct encodings for the get_lane and set_lane variants of vmov.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Added the x86 instruction ud2b (2nd official undefined instruction).Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27JIT imm12 encoding for constant pool entry references.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27SelectionDAG shuffle nodes do not allow operands with different numbers ofBob Wilson
elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27ARM JIT fix for LDRi12 and company.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Provide correct NEON encodings for vdup.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27x86-Win32: Switch ftol2 calling convention from stdcall to C.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117474 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27The new LDR* instruction patterns should handle the necessary encoding ofJim Grosbach
operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Add correct NEON encodings for vsli and vsri.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Add correct NEON encodings for vsra and vrsra.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27The immediate operands of an LDRi12 instruction doesn't need the addrmode2Jim Grosbach
encoding tricks. Handle the 'imm doesn't fit in the insn' case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Yet another tweak to X86 instructions to add ud2a as an alias to ud2Kevin Enderby
(still to add ud2b). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Another tweak to X86 instructions to add the missing flex instruction (withoutKevin Enderby
the wait prefix). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Tweaks to X86 instructions to allow the 'w' suffix in places it makesKevin Enderby
sense, when the instruction takes the 16-bit ax register or m16 memory location. These changes to llvm-mc matches what the darwin assembler allows for these instructions. Done differently than in r117031 that caused a valgrind error which was later reverted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27LDRi12 machine instructions handle negative offset operands normally (simpleJim Grosbach
integer values), not with the addrmode2 encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mcKevin Enderby
will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27One more spot where the new arm mode LDR instruction representationJim Grosbach
doesn't need the additional addrmode2 register operand. Missed it the first time around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Adding disassembler to the MicroBlaze backend.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing onJim Grosbach
rdar://8477752. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Since I parameterized this bit, I should probably actually use said parameter.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Use a MemIntrinsicSDNode for ISD::PREFETCH, which touchesDale Johannesen
memory, so a MachineMemOperand is useful (not propagated into the MachineInstr yet). No functional change except for dump output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and ↵Owen Anderson
vqrshrun. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach
explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Simplify classes for shift instructions, which are never commutable.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Provide correct NEON encodings for vshl, register and immediate forms.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Grammar.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Nuke extraneous comment. It's applicable elsewhere, but not in this func.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Add correct NEON encoding for vpadal.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26handle X86::EH_RETURN64 and X86::EH_RETURN.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Add NEON encodings for vmov and vmvn of immediates.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Implement some relaxations for arithmetic instructions. The limitationRafael Espindola
on RIP relative relocations looks artificial, but this is a superset of what we were able to do before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Change v64 datalayout in SPU.Kalle Raiskila
The SPU ABI does not mention v64, and all examples in C suggest v128 are treated similarily to arrays, we use array alignment for v64 too. This makes the alignment of e.g. [2 x <2 x i32>] behave "intuitively" and similar to as if the elements were e.g. i32s. This also makes an "unaligned store" test to be aligned, with different (but functionally equivalent) code generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26NEON vmov's are in Neon domain.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117347 91177308-0d34-0410-b5e6-96231b3b80d8
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