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2008-11-05Reintroduce a comment that was removed with the AddToISelQueueDan Gohman
changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58760 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05Test commit, add Makefile for XCore target, more to follow.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58755 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05Add more vector move low and zero-extend patterns.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58752 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05Indentation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58750 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05Eliminate the ISel priority queue, which used the topological order for aDan Gohman
priority function. Instead, just iterate over the AllNodes list, which is already in topological order. This eliminates a fair amount of bookkeeping, and speeds up the isel phase by about 15% on many testcases. The impact on most targets is that AddToISelQueue calls can be simply removed. In the x86 target, there are two additional notable changes. The rule-bending AND+SHIFT optimization in MatchAddress that creates new pre-isel nodes during isel is now a little more verbose, but more robust. Instead of either creating an invalid DAG or creating an invalid topological sort, as it has historically done, it can now just insert the new nodes into the node list at a position where they will be consistent with the topological ordering. Also, the address-matching code has logic that checked to see if a node was "already selected". However, when a node is selected, it has all its uses taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any further visits from MatchAddress. This code is now removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05Use getTargetConstant instead of getConstant for nodes that should not be ↵Dan Gohman
visited by isel and potentially forced into registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58747 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05Rename isGVLazyPtr to isGVNonLazyPtr relocation. This represents Mac OS XEvan Cheng
indirect gv reference. Please don't call it lazy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58746 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58725 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with ↵Evan Cheng
legalizetypes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58714 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04Debug output tweak.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58708 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58707 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04For some targets, it's not possible to place GVs in the same memory buffer ↵Evan Cheng
as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements. This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58688 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04Stylistic change.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58683 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-04Handle ARM machine constantpool entries.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58671 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-03The ANDMask node folds to a constant, and isn't the node that needs toDan Gohman
have its node id set. The new and and shift nodes are the nodes that need the IDs. This fixes PR2982. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58655 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-03Remove a dead switch statement.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58644 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-03Minor code restructuring. No functionality change.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58643 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-03Add binary encoding support for multiply instructions. Some blanks left to ↵Jim Grosbach
fill in, but the basics are there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-03Refactor various TargetAsmInfo subclasses' TargetMachine members awayDan Gohman
adding a TargetMachine member to the base TargetAsmInfo class instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58624 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Whitespace fixes. No functionality change.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58539 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Add comment.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58533 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Use better data structure for ConstPoolId2AddrMap.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58532 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Actually make debug output understandable.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58529 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31x86_64 rip-relative and magic mode addressMon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58528 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Forgot this in last commit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58527 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Encode PICADD; some code clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Revert r58489. It isn't correct for all cases.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58523 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Change x86 register allocation ordering to match that of gcc. Otherwise some ↵Evan Cheng
tools get confused by prologue generated by llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58517 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Don't skip over all "terminator" instructions when determining where to put theBill Wendling
callee-saved restore code. It could skip over conditional jumps accidentally. Instead, just skip the "return" instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58489 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-31Use MOVSSmr instead of EXTRACTPSmr in the case of extractingDan Gohman
vector element 0 for a store, as it's smaller and faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58483 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-30I think we got non-machine specific constpool entries covered.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58474 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-30Shift amounts should have type getShiftAmountTyDuncan Sands
(i32 for PPC, not i8). Correct this, and some formatting while there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58451 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-30Shift amounts should have the type given byDuncan Sands
getShiftAmountTy (i32 in the case of CellSPU). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58449 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-30ARM JIT should observe -relocation-model command line option.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58433 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-30Add initial support for vector widening. Logic is set to widen for X86.Mon P Wang
One will only see an effect if legalizetype is not active. Will move support to LegalizeType soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58426 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-30Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stackScott Michel
so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU. N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is still unexorcised code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58415 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-29Correct way to handle CONSTPOOL_ENTRY instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58409 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-29Add debugging support.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58408 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-29Fix PEXTRQ encodingNate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58403 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-29Add a RM pseudoreg for the rounding mode, whichDale Johannesen
allows ppcf128->int conversion to work with DeadInstructionElimination. This is now turned off but RM is harmless. It does not do a complete job of modeling the rounding mode. Revert marking MFCR as using all 7 CR subregisters; while correct, this caused the problem in PR 2964, plus the local RA crash noted in the comments. This was needed to make DeadInstructionElimination, but as we are not running that, it is backed out for now. Eventually it should go back in and the other problems fixed where they're broken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58391 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-28Support for constant islands in the ARM JIT.Jim Grosbach
Since the ARM constant pool handling supercedes the standard LLVM constant pool entirely, the JIT emitter does not allocate space for the constants, nor initialize the memory. The constant pool is considered part of the instruction stream. Likewise, when resolving relocations into the constant pool, a hook into the target back end is used to resolve from the constant ID# to the address where the constant is stored. For now, the support in the ARM emitter is limited to 32-bit integer. Future patches will expand this to the full range of constants necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58338 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-28Fix darwin ppc llvm-gcc build breakage: interceptDuncan Sands
ppcf128 to i32 conversion and expand it into a code sequence like in LegalizeDAG. This needs custom ppc lowering of FP_ROUND_INREG, so turn that on and make it work with LegalizeTypes. Probably PPC should simply custom lower the original conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58329 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-28Fix a nasty miscompilation of 176.gcc on linux/x86 where we synthesizedChris Lattner
a memset using 16-byte XMM stores, but where the stack realignment code didn't work. Until it does (PR2962) disable use of xmm regs in memcpy and memset formation for linux and other targets with insufficiently aligned stacks. This is part of PR2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58317 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27Have TableGen emit setSubgraphColor calls under control of a -gen-debugDavid Greene
flag. Then in a debugger developers can set breakpoints at these calls to see waht is about to be selected and what the resulting subgraph looks like. This really helps when debugging instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58278 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27For now, don't split live intervals around x87 stack register barriers. ↵Evan Cheng
FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-25Move the code that adds the DeadMachineInstructionElimPass fromDan Gohman
target-independent code to target-specific code. This prevents it from running on targets that aren't using fast-isel. In addition to saving compile time, this addresses the problem that not all targets are prepared for it. In order to use this pass, all instructions must declare all their fixed uses and defs of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58144 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-25Support for allocation of TLS variables in the JIT. Allocation of a globalNicolas Geoffray
variable is moved to the execution engine. The JIT calls the TargetJITInfo to allocate thread local storage. Currently, only linux/x86 knows how to allocate thread local global variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58142 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-25Generate code for TLS instructions.Nicolas Geoffray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58141 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-25CMake: lib/Target/ARM/AsmPrinter/CMakeLists.txt added.Oscar Fuentes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58133 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-24Mark MFCR as reading all condition code registers.Dale Johannesen
Prevents some more overzealous deletions (mostly in AltiVec code). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58121 91177308-0d34-0410-b5e6-96231b3b80d8
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