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2004-10-07Remove unnecessary header includeNate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16824 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06Correct some typeosChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16770 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06Remove debugging code, fix encoding problem. This fixes the problemsChris Lattner
the JIT had last night. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16766 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06Turning on fsel code gen now that we can do so would be good.Nate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16765 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06Implement floating point select for lt, gt, le, ge using the powerpc fselNate Begeman
instruction. Now, rather than emitting the following loop out of bisect: .LBB_main_19: ; no_exit.0.i rlwinm r3, r2, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f2, f2, f1 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fcmpu cr0, f1, f4 bge .LBB_main_64 ; no_exit.0.i .LBB_main_63: ; no_exit.0.i b .LBB_main_65 ; no_exit.0.i .LBB_main_64: ; no_exit.0.i fmr f2, f1 .LBB_main_65: ; no_exit.0.i addi r3, r2, 1 rlwinm r3, r3, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f4, f4, f1 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3) fcmpu cr0, f1, f5 bge .LBB_main_67 ; no_exit.0.i .LBB_main_66: ; no_exit.0.i b .LBB_main_68 ; no_exit.0.i .LBB_main_67: ; no_exit.0.i fmr f4, f1 .LBB_main_68: ; no_exit.0.i fadd f1, f2, f4 addis r3, r30, ha16(.CPI_main_2-"L00000$pb") lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3) fmul f1, f1, f2 rlwinm r3, r2, 3, 0, 28 lfdx f2, r3, r28 fadd f4, f2, f1 fcmpu cr0, f4, f0 bgt .LBB_main_70 ; no_exit.0.i .LBB_main_69: ; no_exit.0.i b .LBB_main_71 ; no_exit.0.i .LBB_main_70: ; no_exit.0.i fmr f0, f4 .LBB_main_71: ; no_exit.0.i fsub f1, f2, f1 addi r2, r2, -1 fcmpu cr0, f1, f3 blt .LBB_main_73 ; no_exit.0.i .LBB_main_72: ; no_exit.0.i b .LBB_main_74 ; no_exit.0.i .LBB_main_73: ; no_exit.0.i fmr f3, f1 .LBB_main_74: ; no_exit.0.i cmpwi cr0, r2, -1 fmr f16, f0 fmr f17, f3 bgt .LBB_main_19 ; no_exit.0.i We emit this instead: .LBB_main_19: ; no_exit.0.i rlwinm r3, r2, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f2, f2, f1 fsel f1, f1, f1, f2 addi r3, r2, 1 rlwinm r3, r3, 3, 0, 28 lfdx f2, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f4, f4, f2 fsel f2, f2, f2, f4 fadd f1, f1, f2 addis r3, r30, ha16(.CPI_main_2-"L00000$pb") lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3) fmul f1, f1, f2 rlwinm r3, r2, 3, 0, 28 lfdx f2, r3, r28 fadd f4, f2, f1 fsub f5, f0, f4 fsel f0, f5, f0, f4 fsub f1, f2, f1 addi r2, r2, -1 fsub f2, f1, f3 fsel f3, f2, f3, f1 cmpwi cr0, r2, -1 fmr f16, f0 fmr f17, f3 bgt .LBB_main_19 ; no_exit.0.i git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16764 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06Codegen signed mod by 2 or -2 more efficiently. Instead of generating:Chris Lattner
t: mov %EDX, DWORD PTR [%ESP + 4] mov %ECX, 2 mov %EAX, %EDX sar %EDX, 31 idiv %ECX mov %EAX, %EDX ret Generate: t: mov %ECX, DWORD PTR [%ESP + 4] *** mov %EAX, %ECX cdq and %ECX, 1 xor %ECX, %EDX sub %ECX, %EDX *** mov %EAX, %ECX ret Note that the two marked moves are redundant, and should be eliminated by the register allocator, but aren't. Compare this to GCC, which generates: t: mov %eax, DWORD PTR [%esp+4] mov %edx, %eax shr %edx, 31 lea %ecx, [%edx+%eax] and %ecx, -2 sub %eax, %ecx ret or ICC 8.0, which generates: t: movl 4(%esp), %ecx #3.5 movl $-2147483647, %eax #3.25 imull %ecx #3.25 movl %ecx, %eax #3.25 sarl $31, %eax #3.25 addl %ecx, %edx #3.25 subl %edx, %eax #3.25 addl %eax, %eax #3.25 negl %eax #3.25 subl %eax, %ecx #3.25 movl %ecx, %eax #3.25 ret #3.25 We would be in great shape if not for the moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16763 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06Really fix FreeBSD, which apparently doesn't tolerate the extern.Chris Lattner
Thanks to Jeff Cohen for pointing out my goof. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16762 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06Fix a scary bug with signed division by a power of two. We used to generate:Chris Lattner
s: ;; X / 4 mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, %EAX sar %ECX, 1 shr %ECX, 30 mov %EDX, %EAX add %EDX, %ECX sar %EAX, 2 ret When we really meant: s: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, %EAX sar %ECX, 1 shr %ECX, 30 add %EAX, %ECX sar %EAX, 2 ret Hey, this also reduces register pressure too :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16761 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06Codegen signed divides by 2 and -2 more efficiently. In particularChris Lattner
instead of: s: ;; X / 2 movl 4(%esp), %eax movl %eax, %ecx shrl $31, %ecx movl %eax, %edx addl %ecx, %edx sarl $1, %eax ret t: ;; X / -2 movl 4(%esp), %eax movl %eax, %ecx shrl $31, %ecx movl %eax, %edx addl %ecx, %edx sarl $1, %eax negl %eax ret Emit: s: movl 4(%esp), %eax cmpl $-2147483648, %eax sbbl $-1, %eax sarl $1, %eax ret t: movl 4(%esp), %eax cmpl $-2147483648, %eax sbbl $-1, %eax sarl $1, %eax negl %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16760 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06Add some new instructions. Fix the asm string for sbb32rrChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16759 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-06FreeBSD uses GCC. Patch contributed by Jeff Cohen!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16756 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-04* Prune #includesChris Lattner
* Update comments * Rearrange code a bit * Finally ELIMINATE the GAS workaround emitter for Intel mode. woot! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16647 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-04Add support for emitting AT&T style .s files, and make it the default. UsersChris Lattner
may now choose their output format with the -x86-asm-syntax={intel|att} flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16646 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-04Convert some missed patterns to support AT&T styleChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16645 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-04Apparently the GNU assembler has a HUGE hack to be compatible with reallyChris Lattner
old and broken AT&T syntax assemblers. The problem with this hack is that *SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted. This was a real pain to figure out, but is trivially easy to support: thus we are now bug compatible with gas and gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16644 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-04Fix incorrect suffixChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16642 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-04Fix some more missed suffixes and swapped operandsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16641 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-04Add missing suffixes to FP instructions for AT&T modeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16640 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-03Add support for the -x86-asm-syntax flag, which can be used to choose betweenChris Lattner
Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16639 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-03Add support to the instruction patterns for AT&T style output, which willChris Lattner
hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also includes changes to wrap the whole file to 80 columns! Woot! :) Note that the AT&T style output has not been tested at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16638 91177308-0d34-0410-b5e6-96231b3b80d8
2004-10-03Add initial support for variantsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16635 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-30Make EmitMappingInfo into an "external location" option, so that it can be setBrian Gaeke
or cleared externally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16623 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-30I think this will handle double args.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16618 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-30Mark the instructions that have delay slots with the hasDelaySlot flag.Brian Gaeke
Add some comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16611 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-30Use TargetMachine::hasDelaySlot() instead of our old switch statementBrian Gaeke
to find instrs that have delay slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16610 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Change the #ifdefs to allow compilation with a V8 compiler, but the JIT stillMisha Brukman
won't work if not compiled in V9 mode, currently by GCC only, because Sun's system compiler does not tell us if it's a V8 or V9 system. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16602 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Update list of shootout programs that should be working.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16595 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Tell the target description that calls clobber registers O0...O5.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16594 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29FITOD is spelled "fitod", not "fitos". Ouch.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16591 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Don't use .quad to output double constants. The assembler must have a bug orBrian Gaeke
something, because the wrong bit patterns get output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16590 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Recognize FpMOVD as a move.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16586 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Generate better code by being far less clever when it comes to the select ↵Nate Begeman
instruction. Don't create overlapping register lifetimes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16580 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29add resultsBrian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16579 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29improve Type::BoolTy codegen by eliminating unnecessary clears and sign extendsNate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16578 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Simplify copyConstantToRegister() for longs, using a pair of recursive calls.Brian Gaeke
Copy constant-pool entries' addresses into registers before loading out of them, to avoid errors from the assembler. Handle loading call args past the 6th one off the stack. Add IMPLICIT_DEF pseudo-instrs for double and long arguments passed in register pairs. Use FpMOVD to copy doubles around instead of the horrible store-load thing we were doing before. Handle 'ret double' and 'ret long'. Fix a bug in handling 'and/or/xor long'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16577 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Fix bug recognizing moves: isMoveInstr should only treat ORs with %g0 asBrian Gaeke
moves, not all ORs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16576 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Use FpMOVD pseudo-instruction to move doubles around.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16575 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Add new FpMOVD pseudo-instruction, used to move doubles around.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16574 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Fix double and long alignment.Brian Gaeke
Call the FPMover pass after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16573 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Put quotes around argument to .section directive.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16572 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Add createSparcV8FPMoverPass().Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16571 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29Pass which converts FpMOVD (double move pseudoinstructions) to pairsBrian Gaeke
of FMOVS instrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16570 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-29To go along with sabre's improved InstCombining, improve recognition ofNate Begeman
integers that we can use as immediate values in instructions. Example from yacr2: - lis r10, -1 - ori r10, r10, 65535 - add r28, r28, r10 + addi r28, r28, -1 addi r7, r7, 1 addi r9, r9, 1 b .LBB_main_9 ; loopentry.1.i214 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16566 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28Add support for the isLoad and isStore flags, needed by the instruction ↵Nate Begeman
scheduler git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16555 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28Capture delay slot infoChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16551 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28Add includes and use std:: for standard library calls to make codeAlkis Evlogimenos
compile on windows. This patch was contributed by Paolo Invernizzi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16539 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28Since we use alloca now make sure we include the proper headers for it.Alkis Evlogimenos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16536 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28Use alloca instead of a C99 style array. This should fix theAlkis Evlogimenos
compilation problem in windows. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16535 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-28Pull assignment out of for loop conditional in order for this toAlkis Evlogimenos
compile under windows. Patch contributed by Paolo Invernizzi! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16534 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-27SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned!Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16526 91177308-0d34-0410-b5e6-96231b3b80d8
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