aboutsummaryrefslogtreecommitdiff
path: root/lib/Target
AgeCommit message (Collapse)Author
2010-04-21Modified some assert() msg strings; no other functionality change.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21Implement -disable-non-leaf-fp-elim which disable frame pointer eliminationEvan Cheng
optimization for non-leaf functions. This will be hooked up to gcc's -momit-leaf-frame-pointer option. rdar://7886181 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21Trim include.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21Add more const qualifiers on TargetMachine and friends.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21Thumb instructions which have reglist operands at the end and predicate operandsJohnny Chen
before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21Handle a displacement location in 64-bit as an RIP-relative displacement. ItBill Wendling
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work: target triple = "x86_64-apple-darwin" define double @func(double %a) { %tmp1 = fmul double %a, 5.000000e-01 ; <double> [#uses=1] ret double %tmp1 } define i32 @main() nounwind { %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0] ret i32 0 } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101965 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20teach the x86 address matching stuff to handleChris Lattner
(shl (or x,c), 3) the same as (shl (add x, c), 3) when x doesn't have any bits from c set. This finishes off PR1135. Before we compiled the block to: to: LBB0_3: ## %bb cmpb $4, %dl sete %dl addb %dl, %cl movb %cl, %dl shlb $2, %dl addb %r8b, %dl shlb $2, %dl movzbl %dl, %edx movl %esi, (%rdi,%rdx,4) leaq 2(%rdx), %r9 movl %esi, (%rdi,%r9,4) leaq 1(%rdx), %r9 movl %esi, (%rdi,%r9,4) addq $3, %rdx movl %esi, (%rdi,%rdx,4) incb %r8b decb %al movb %r8b, %dl jne LBB0_1 Now we produce: LBB0_3: ## %bb cmpb $4, %dl sete %dl addb %dl, %cl movb %cl, %dl shlb $2, %dl addb %r8b, %dl shlb $2, %dl movzbl %dl, %edx movl %esi, (%rdi,%rdx,4) movl %esi, 8(%rdi,%rdx,4) movl %esi, 4(%rdi,%rdx,4) movl %esi, 12(%rdi,%rdx,4) incb %r8b decb %al movb %r8b, %dl jne LBB0_1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101958 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20Because of the EMMS problem, right now we have to supportDale Johannesen
user-defined operations that use MMX register types, but the compiler shouldn't generate them on its own. This adds a Synthesizable abstraction to represent this, and changes the vector widening computation so it won't produce MMX types. (The motivation is to remove noise from the ABI compatibility part of the gcc test suite, which has some breakage right now.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),Johnny Chen
instead of just asserting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if ↵Johnny Chen
Rn(Inst{19-16})=='1111', transform the Opcode to the corresponding t2LDR*pci counterpart. Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20teach cellspu how to return i8 and i16 from calls,Chris Lattner
patch by Kalle Raiskila! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20disable optimizations in this directory for MSVC9. This avoidsChris Lattner
an optimizer infinite loop on the file, PR6866. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands whereJohnny Chen
d==15 is considered illegal. Return false instead of assert(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20Remove the palignr intrinsics now that we lower them to vector shuffles,Eric Christopher
shifts and null vectors. Autoupgrade these to what we'd lower them to. Add a testcase to exercise this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20More IT instruction error-handling improvements from fuzzing.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19Better error handling of invalid IT mask '0000', instead of just asserting.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19Delete an unnecessary reference to SelectionDAGISel::BB.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1Johnny Chen
Pseudocode details of conditional, Condition bits '111x' indicate the instruction is always executed. That is, '1111' is a leagl condition field value, which is now mapped to ARMCC::AL. Also add a test case for condition field '1111'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19More progress on promoting i16 operations to i32 for x86. Work in progress.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operandJohnny Chen
instructions should have Rd (Inst{11-8}) != 0b1111. Ref: A6.3 32-bit Thumb instruction encoding A6.3.11 Data-processing (shifted register) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19ARM disassembler did not react to recent changes to the NEON instruction table.Johnny Chen
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18Add missed part of prev. commitAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18Make processor FUs unique for given itinerary. This extends the limit of 32Anton Korobeynikov
FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17fix PR6332, allowing an index of zero into a zero sized array Chris Lattner
even if the element of the array has no size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17teach the x86 asm parser how to handle segment prefixesChris Lattner
in memory operands. rdar://7874844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Fix -Wcast-qual warnings.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17remove a dead variable, PR6856Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Add const qualifiers to TargetLoweringObjectFile usage.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Use const_cast instead of a C-style cast to cast away const.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101639 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Delete now-unnecessary const_casts.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101637 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Use cast instead of dyn_cast when assuming success.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101636 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Use const qualifiers with TargetLowering. This eliminates severalDan Gohman
const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Move per-function state out of TargetLowering subclasses and intoDan Gohman
MachineFunctionInfo subclasses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Name these stub files consistently with the SPU and PPC targets' conventions.Chandler Carruth
Also rename the classes appropriately. The CMake build already used these names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101631 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17a bunch of ssse3 instructions are misencoded to think they have an Chris Lattner
i8 field when they really do not. This fixes rdar://7840289 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17More work to allow dag combiner to promote 16-bit ops to 32-bit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that thisBob Wilson
may be called when either the source or destination type is i64, and my change also hadn't fixed the most obvious problem -- assuming that i64 will only be bitconverted to f64, ignoring the various vector types. Radar 7873160. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16add a noteChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101581 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Revert 101465, it broke internal OpenGL testing.Eric Christopher
Probably the best way to know that all getOperand() calls have been handled is to replace that API instead of updating. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101579 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Cast to (uint64_t) instead of relying on the "ul" suffix.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Add skeleton target-specific SelectionDAGInfo files.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Fixed logic error. Should check Builder for validity before calling SetSessionJohnny Chen
on it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16add a missing break back, patch by Nico Schmidt!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16In the same spirit of r101524, which removed the assert() from ↵Johnny Chen
printAddrMode2OffsetOperand(), this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. ChangedJohnny Chen
to the UAL syntax of LDCL<c>, instead. Add a test case for this change which also tests the removal of assert() from printAddrMode2OffsetOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" areJohnny Chen
considered legal instructions. Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM) -- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16reapply r101434Gabor Greif
with a fix for self-hosting rotate CallInst operands, i.e. move callee to the back of the operand array the motivation for this patch are laid out in my mail to llvm-commits: more efficient access to operands and callee, faster callgraph-construction, smaller compiler binary git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101465 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-05-04 22:40:49 +0000