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2010-03-03Eliminate unused instruction classes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy forJohnny Chen
disassembly only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97614 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02merge two loops over all nodes in the graph into one.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02eliminate PreprocessForRMW now that isel handles it.Chris Lattner
We still preprocess calls and fp return stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97598 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02remove 300 lines of code that is now dead in the MSP430 backendChris Lattner
now that isel handles chains more aggressively. This also allows us to make isLegalToFold non-virtual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Fix some issues in WalkChainUsers dealing with Chris Lattner
CopyToReg/CopyFromReg/INLINEASM. These are annoying because they have the same opcode before an after isel. Fix this by setting their NodeID to -1 to indicate that they are selected, just like what automatically happens when selecting things that end up being machine nodes. With that done, give IsLegalToFold a new flag that causes it to ignore chains. This lets the HandleMergeInputChains routine be the one place that validates chains after a match is successful, enabling the new hotness in chain processing. This smarter chain processing eliminates the need for "PreprocessRMW" in the X86 and MSP430 backends and enables MSP to start matching it's multiple mem operand instructions more aggressively. I currently #if out the dead code in the X86 backend and MSP backend, I'll remove it for real in a follow-on patch. The testcase changes are: test/CodeGen/X86/sse3.ll: we generate better code test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was miscompiling this before, we now generate correct code Convert it to filecheck while I'm at it. test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem folding to make anton happy. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97596 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97595 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as fromJohnny Chen
the opc string passed in, since it's a given from the class inheritance of T2sI. The fixed the extra 's' in adcss & sbcss when disassembly printing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,Johnny Chen
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for disassembly only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02AL is an optional mnemonic extension for always, except in IT instructions.Johnny Chen
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing. Ref: A8.3 Conditional execution git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Change some asm shift opcode strings to lowercase.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02fix typo add missing (Xerxes Ranby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97565 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Unbreak llvm-arm-linux buildbot and fix PR5309.Xerxes Ranby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Sink InstructionSelect() out of each target into SDISel, and rename itChris Lattner
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader. Sink some other stuff out of DAGISelHeader into SDISel. Eliminate the various 'Indent' stuff from various targets, which dates to when isel was recursive. 17 files changed, 114 insertions(+), 430 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Only save vector registers if we've defined for the vector registers.Eric Christopher
Fixes PR5309. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Remove dead parameter passing.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Floating-point add, sub, and mul are now spelled fadd, fsub, and fmul,Dan Gohman
respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01remove a little hack I did for the old isel, not neededChris Lattner
now that it is gone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97516 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01Remove the optimize for code size limitation on r67917. Optimize 64-bit imul ↵Evan Cheng
by constants into leas + shl regardless if optimizing for code size. The size saving from using imulq isn't worth it. Also, the lea and shl instructions may expose further optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01remove a terrible hack that disabled assertions from this file because of ↵Chris Lattner
build time problems. rdar://7697850. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01stop using generated sdnodexforms.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the WJohnny Chen
bit should be set to 0 instead of 1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01Add explicit keywords.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01This is now done.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01Add JIT support to the TODO list (test commit)Nathan Keynes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-2880-col violations/trailing whitespace.Mikhail Glushenkov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-28remove redundant instruction.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-28Add a flag to addPassesToEmit* to disable the Verifier pass runDan Gohman
after LSR, so that clients can opt in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-28Implement XMM subregs.Dan Gohman
Extracting the low element of a vector is now done with EXTRACT_SUBREG, and the zero-extension performed by load movss is now modeled with SUBREG_TO_REG, and so on. Register-to-register movss and movsd are no longer considered copies; they are two-address instructions which insert a scalar into a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27The mayHaveSideEffects flag is no longer used.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27remove a bogus pattern, which had the same pattern as STDUChris Lattner
but codegen'd differently. This really wanted to use some sort of subreg to get the low 4 bytes of the G8RC register or something. However, it's invalid and nothing is testing it, so I'm just zapping the bogosity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97345 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27fix an incorrect (overly conservative) predicate.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97316 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-27Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Added the follwoing 32-bit Thumb instructions for disassembly only:Johnny Chen
o Parallel addition and subtraction, signed/unsigned o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8 o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16 o Signed multiply accumulate long (halfwords): SMLAL<x><y> o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X] o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Merge PPC instructions FMRS and FMRD into a single FMR instruction.Jakob Stoklund Olesen
This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so fextend has a pattern. Also allow folding of memory operands on FMRSD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Use the right floating point load/store instructions in ↵Jakob Stoklund Olesen
PPCInstrInfo::foldMemoryOperandImpl(). The PowerPC floating point registers can represent both f32 and f64 via the two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to allow cross-class coalescing. This coalescing only affects whether registers are spilled as f32 or f64. Spill slots must be accessed with load/store instructions corresponding to the class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking at the instruction opcode which is wrong. X86 has similar floating point register classes, but doesn't try to fold memory operands, so there is no problem there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97262 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Move dbg_value generation to target-independent FastISel,Dale Johannesen
as X86 is currently the only FastISel target. Per review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97255 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26The cloner has nothing to do if any of the main or ISR entrypoints are not Sanjiv Gupta
present in the module. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Reapply things reverted back in 97220, with the fixed test case.Sanjiv Gupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26movl is a cheaper way to materialize 0 without clobbering EFLAGS than movabsq.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy.Richard Osborne
Previously LoopStrengthReduce would sometimes be unable to find a legal formula, causing an assertion failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Revert r97211 and r97213 to get the build green again.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Currently in LLVM, names of libcalls are assigned during TargetLoweringSanjiv Gupta
object construction. There is no provision to change them when the code for a function generated. So we have to change these names while printing assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97213 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Before converting an operand to mem, check if it is legal to do so.Sanjiv Gupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-26Delete a bunch of redundant predicates.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,Johnny Chen
and SRS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25Added the 32-bit Thumb instructions (BXJ) for disassembly only.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97159 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25Fix TextAlignFillValue in a few placesDaniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-25Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,Johnny Chen
WFI, SEV, SETEND. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97149 91177308-0d34-0410-b5e6-96231b3b80d8
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