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2010-11-10Simplify and clean up MC symbol lookup for ARM constant pool values. This fixesJim Grosbach
double quoting of ObjC symbol names in constant pool entries. rdar://8652107 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10Update ARMConstantPoolValue to not use a modifier string. Use an explicitJim Grosbach
VariantKind marker to indicate the additional information necessary. Update MC to handle the new Kinds. rdar://8647623 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some ↵Bruno Cardoso Lopes
minor tweaks git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10Emit a '!' if this is a "writeback" register or memory address.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10Rename a parameter to avoid confusion with a local variableMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Emit the warning about the register list not being in ascending order only once.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09s/std::vector/SmallVector/Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Delete the allocated vector.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Define the subtarget feature for the architecture version,Bob Wilson
as derived from the target triple. This is important for enabling features that are implied based on the architecture version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson
It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Two types of instructions have register lists:Bill Wendling
* LDM, et al, uses a bit mask to indicate the register list. * VLDM, et al, uses a base register plus number. The LDM instructions may be non-contiguous, but the VLDM ones must be contiguous. Those are semantic checks that should be done later in the compiler. Also postpone the creation of the bit mask until it's needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Change the ARMConstantPoolValue modifier string to an enumeration. This willJim Grosbach
help in MC'izing the references that use them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Handle ARM constant pool values that need an explicit reference to the '.'Jim Grosbach
pseudo-label. (TLS stuff). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09add a case we fail to devirt.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Further MCize ARM constant pool values. This allows basic PIC references forJim Grosbach
object file emission. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09For ARM load/store instructions, encode [reg+reg] with no shifter immediate asJim Grosbach
a left shift by zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09ARM .word data fixups don't need an adjustment.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Fix trailing whitespace and style, no functionality changeBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Add support for a few simple fixups to the ARM Darwin asm backend. This allowsJim Grosbach
constant pool references and global variable refernces to resolve properly for object file generation. For example, int x; void foo(unsigned a, unsigned *p) { p[a] = x; } can now be successfully compiled directly to an (ARM mode) object file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Revert r118457 and r118458. These won't hold for GPRs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Get the register and count from the register list operands.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08reglist has two operands.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08The "addRegListOperands()" function returns the start register and the totalBill Wendling
number of registers in the list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka ↵Bruno Cardoso Lopes
(ahatanaka@mips.com) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Add "write back" bit encoding.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Fix PR8211Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118445 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Adding working version of assembly parser for the MBlaze backendWesley Peck
Major cleanup of whitespace and formatting issues in MBlaze backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Revert 118422 in search of bot verdancy.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Complete listing of ARM/MC/ELF relocation enumsJason W Kim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Add generating function declaration for PTXChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Add physical register counting functionsChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118397 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Add a dummy PTXMCAsmStreamer classChe-Liang Chiou
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Make RegList an ASM operand so that TableGen will generate code for it. This isBill Wendling
an initial implementation and may change once reglists are fully fleshed out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Revert.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-07Fix a README item: when doing a comparison with the resultDuncan Sands
of a select instruction, see if doing the compare with the true and false values of the select gives the same result. If so, that can be used as the value of the comparison. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-07In this context, a reglist is a reg.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06implement aliases for div/idiv that have an explicit A register operand,Chris Lattner
implementing rdar://8431864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06Add support for parsing register lists. We can't use a bitfield to keep track ofBill Wendling
the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06add aliases for movs between seg registers and mem. There are multipleChris Lattner
different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06Return the base register of a register list for the "getReg()" method. This isBill Wendling
to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06work-in-progressChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06General cleanup:Bill Wendling
- Make ARMOperand a class so that some things are internal to the class. - Reformatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06go to great lengths to work around a GAS bug my previous patchChris Lattner
exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06rework the rotate-by-1 instructions to be defined like theChris Lattner
shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
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