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2012-04-27X86: Don't emit conditional floating point moves on when targeting ↵Benjamin Kramer
pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton
the mask operand in the MCInst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27Implement a bastardized ABI.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng
instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach
The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Trivial change to set UseLeaForSP flag in addition to togglingPreston Gurd
the FeatureLeaForSP feature bit when llvm auto detects Intel Atom. Patch by Andy Zhang git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Use VLD1 in NEON extenting-load patterns instead of VLDR.Tim Northover
On some cores it's a bad idea for performance to mix VFP and NEON instructions and since these patterns are NEON anyway, the NEON load should be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Test commit.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to ↵Craig Topper
corei7-avx, core-avx-i, and core-avx2 cpu names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng
the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Unify internal representation of ARM instructions with a register ↵Richard Barton
right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper
only targets that want the function get it. This prevents other targets from getting an unused function warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Use vector_shuffles instead of target specific unpack nodes for AVX ↵Craig Topper
ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Do not use $gp as a dedicated global register if the target ABI is not O32. Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155522 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach
When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24ARM: Nuke remnant bogus code.Jim Grosbach
r154362 was supposed to delete this bit, but obviously didn't. rdar://11305594 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX: Add additional vbroadcast replacement sequences for integers.Nadav Rotem
Remove the v2f64 patterns because it does not match any vbroadcast instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8Nadav Rotem
immediate. We can't use it here because the shuffle code does not check that the lower part of the word is identical to the upper part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155440 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Refactor Thumb ITState handling in ARM Disassembler to more efficiently use ↵Richard Barton
its vector git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155439 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructionsNadav Rotem
using the pattern (vbroadcast (i32load src)). In some cases, after we generate this pattern new users are added to the load node, which prevent the selection of the blend pattern. This commit provides fallback patterns which perform in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155437 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Remove dangling spaces. Fix some other formatting.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Simplify code a bit and make it compile better. Remove unused parameters.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Tidy up. 80 columns, whitespace, et. al.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155399 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Optimize the vector UINT_TO_FP, SINT_TO_FP and FP_TO_SINT operations where ↵Nadav Rotem
the integer type is i8 (commonly used in graphics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155397 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd
on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23ARM: VSLI two-operand assmebly aliases are tblgen'erated.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155393 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23ARM: tblgen'erate VSRA/VRSRA/VSRI assembly two-operand aliases.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155392 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23ARM: vqdmulh two-operand aliases are tblgen'erated now.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155387 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Hexagon V5 (floating point) support.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Support for Hexagon architectural feature, new value jump.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Support for Hexagon VLIW Packetizer.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155365 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Use MVT instead of EVT through all of LowerVECTOR_SHUFFLEtoBlend and not ↵Craig Topper
just the switch. Saves a little bit of binary size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155339 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Make getZeroVector and getOnesVector more alike as far as how they detect ↵Craig Topper
128-bit versus 256-bit vectors. Be explicit about both sizes and use llvm_unreachable. Similar changes to getLegalSplat. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155337 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Tidy up by removing some 'else' after 'return'Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Tidy up spacing in LowerVECTOR_SHUFFLEtoBlend. Remove code that checks if ↵Craig Topper
shuffle operand has a different type than the the shuffle result since it can never happen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155333 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Add a couple llvm_unreachables.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155332 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Remove some tab characers.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23Remove some 'else' after 'return'. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22Make Extract128BitVector and Insert128BitVector take an unsigned instead of ↵Craig Topper
an ConstantNode SDValue. getConstant was almost always called just before only to have the functions take it apart and build a new ConstantSDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155325 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22Convert getNode(UNDEF) to getUNDEF.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22Make calls to getVectorShuffle more consistent. Use shuffle VT for calls to ↵Craig Topper
getUNDEF instead of requerying. Use &Mask[0] instead of Mask.data(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22Tidy up. 80 columns and argument alignment.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155319 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22Simplify code by converting multiple places that were manually concatenating ↵Craig Topper
128-bit vectors to use either CONCAT_VECTORS or a helper function. CONCAT_VECTORS will itself be lowered to the same pattern as before. The helper function is needed for concats of BUILD_VECTORs since getNode(CONCAT_VECTORS) will just return a large BUILD_VECTOR and we may be trying to lower large BUILD_VECTORS when this occurs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22ARM: Initialize the HasRAS bit.Benjamin Kramer
Found by valgrind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155313 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22Remove some potential warnings about variables used uninitialized.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-21Make some fixed arrays const. Use array_lengthof in a couple places instead ↵Craig Topper
of a hardcoded number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-21Tidy up. 80 columns and some other spacing issues.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-21llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build ↵NAKAMURA Takumi
on MSVC. Thanks to Andy Gibbs, to report the issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155287 91177308-0d34-0410-b5e6-96231b3b80d8
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