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2010-11-28When emitting a single function with cppgen=function, you don't want to emitNicolas Geoffray
initializers of global variables used in the function. Also make sure to emit the operands of a constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120253 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28Move the PTXMCAsmStreamer class to the .cpp file.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28Define generic 1, 2 and 4 byte pc relative relocations. They are commonRafael Espindola
and at least the 4 byte one will be needed to implement the .cfi_* directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28Add support for NEON VLD2-dup instructions.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28Another minor refactoring for VLD1DUP instructions.Bob Wilson
The op11_8 field is the same for all of them so put it in the instruction classes instead of specifying it separately for each instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28Add entry in getTargetNodeName() for ARMISD::VBICIMM.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27Move more PEI-related hooks to TFIAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27Move callee-saved regs spills / reloads to TFIAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27Lower TLS_addr32 and TLS_addr64.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27Implement the data16 prefix.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120224 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27Refactor. Set alignment bit in VLD1-dup instruction classes.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27Add NEON VLD1-dup instructions (load 1 element to all lanes).Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.Bob Wilson
I added these instructions recently but I have no idea where these "1" values in the NextCycles field came from. As far as I can tell now, these instruction stages are clearly intended to overlap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27MC/Mach-O: Switch to using MachOFormat.h.Daniel Dunbar
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120187 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-26Remove the unused TheTarget member.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-25Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single ↵Rafael Espindola
instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-25Namespacify.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-24Updating MBlaze .mask and .frame directives to match GCC's output and fixing ↵Wesley Peck
regression introduced in 120095 by checking MCStreamer::hasRawTextSupport. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-241. Fixing error where basic block labels were not being printed out when ↵Wesley Peck
they need to be for the MBlaze backend because AsmPrinter::isBlockOnlyReachableByFallthrough does not take into account delay slots. 2. Re-adding .mask and .frame directives in printed assembly. 3. Adding .ent and .end directives in printed assembly. 4. Minor cleanups to MBlaze backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-24Use i8 as SETCC result type for i1 in SPU.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-24Allow for 'fcmp ogt' in SPU.Kalle Raiskila
Fix by Visa Putkinen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120090 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23The srem -> urem transform is not safe for any divisor that's not a power of ↵Benjamin Kramer
two. E.g. -5 % 5 is 0 with srem and 1 with urem. Also addresses Frits van Bommel's comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120049 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23Move the ARM reloc constants to Support/ELF.hJason W Kim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120035 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.Bob Wilson
We need to check if the individual vector elements are sign/zero-extended values. For now this only handles constants values. Radar 8687140. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120034 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23InstCombine: Reduce "X shift (A srem B)" to "X shift (A urem B)" iff B is ↵Benjamin Kramer
positive. This allows to transform the rem in "1 << ((int)x % 8);" to an and. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23Division by pow-of-2 is not cheap on SPU, do it with Kalle Raiskila
shifts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23Implement the rex64 prefix.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120017 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23Produce a relocation for pcrel absolute values. Based on a patch by David Meyer.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120006 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22Remove duplicated constants. Thanks to Jason for noticing it.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22InstCombine: Implement X - A*-B -> X + A*B.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22Fix epilogue codegen to avoid leaving the stack pointer in an invalidEvan Cheng
state. Previously Thumb2 would restore sp from fp like this: mov sp, r7 sub, sp, #4 If an interrupt is taken after the 'mov' but before the 'sub', callee-saved registers might be clobbered by the interrupt handler. Instead, try restoring directly from sp: add sp, #4 Or, if necessary (with VLA, etc.) use a scratch register to compute sp and then restore it: sub.w r4, r7, #8 mov sp, r7 rdar://8465407 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22Fix a bug with extractelement on SPU.Kalle Raiskila
In the attached testcase, the element was never extracted (missing rotate). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22Implement the "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" optimization.Benjamin Kramer
This currently only catches the most basic case, a two-case switch, but can be extended later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22Fix a compiler warning about Kind being used uninitializedDuncan Sands
when assertions are disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119962 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21Pseudos default to 4byte size, let the instruction size field noticeEric Christopher
that branch tables are special. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21Implement ELF object file writing support for the MBlaze backend. Its not ↵Wesley Peck
perfect yet, but it works for many tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21Implement branch analysis in the MBlaze backend.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21Make it a little bit more explicit that the MBlaze backend only supports uptoWesley Peck
32-bit immediate values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21Fix an error in the MBlaze delay slot filler where instructions that alreadyWesley Peck
fill a delay slot are moved to fill a different delay slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21apparently tailcalls are better on darwin/x86-64 than on linux?Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21More Thumb encodings.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21Add encoding for ARM "trap" instruction.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21The "trap" instruction is one of this which doesn't have a condition code. HackBill Wendling
the code to not add a "condition code" if it's trap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21- Give "trap" the correct encoding, at least according to Darwin's assembler.Bill Wendling
- Add comments saying where the encodings for other instructions came from. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21implement PR8524, apparently mainline gas accepts movq as an alias for movdChris Lattner
when transfering between i64 gprs and mmx regs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21add some random notes.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119925 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21Use by-name rather than by-order operand matching for some NEON encodings.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21optimize:Chris Lattner
void a(int x) { if (((1<<x)&8)==0) b(); } into "x != 3", which occurs over 100 times in 403.gcc but in no other program in llvm-test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21tail calls on x86 are implemented.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119920 91177308-0d34-0410-b5e6-96231b3b80d8
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