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2011-10-17ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach
NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Validate target data layout strings.Lang Hames
Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142288 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Use a SmallVector for intrinsic argument types.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Don't renumber the blocks here. This could cause problems later on if anotherBill Wendling
pass renumbers the blocks again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Pseudoinstructions should not be less constrained than the instruction they areCameron Zwarich
lowered to. This fixes a lot of verifier failures on the test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Tidy up organization.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add a call to EmitSjLjDispatchBlock.Bill Wendling
Once the intrinsics are marked as having a custom inserter, it will call this method to emit the dispatch table into the machine function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Fix improperly formed assert() call.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142239 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add definitions of conditional moves with 64-bit operands. Comment out code forAkira Hatanaka
expanding conditional moves, which is not needed since architectures that lack support for conditional moves have been removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Revert change to function alignment b/c existing logic was fineHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142224 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Removed set, but unused variables.Chad Rosier
Patch by Joe Abbey <jabbey@arxan.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Move class and instruction definitions for conditional moves to a seperate file.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Revert change made in r142205.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Redefine count-leading 0s and 1s instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142216 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Redefine mfhi/lo and mthi/lo instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142214 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Redefine multiply and divide instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add definition of a base class for logical shift/rotate instructions with twoAkira Hatanaka
source registers and redefine 32-bit and 64-bit instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142210 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Remove >80-col line and unicodeHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142209 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add definition of a base class for logical shift/rotate immediate instructionsAkira Hatanaka
and have 32-bit and 64-bit instructions derive from it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142207 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142205 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Fix CMake build.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cppDevang Patel
There is no reason to have simple IR level pass in lib/Target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Instructions for Book E PPC should be word aligned, set function alignment ↵Hal Finkel
to reflect this git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means ↵Craig Topper
that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add comment explaining that the order of processing doesn't matter here.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add PPC 440 scheduler and some associated tests (new files)Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Add PPC 440 scheduler and some associated testsHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 PEXTR and PDEP instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing.Benjamin Kramer
<stdin>:1:12: error: register %rax is only available in 64-bit mode incl %rax ^~~~ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and ↵Benjamin Kramer
print ranges for invalid operands. <stdin>:1:4: error: invalid instruction mnemonic 'abc' abc incl %edi ^~~ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there wasNadav Rotem
no pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper
VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.Cameron Zwarich
These missing flags show up as errors when running -verify-coalescing on test-suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Fix an obvious typo found when looking at nearby code.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang ↵Chris Lattner
does. Enhance the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper
3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-16Add X86 feature detection support for BMI instructions. Added new cpuid ↵Craig Topper
function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142089 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper
because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15The CELL backend cannot select patterns for vector trunc-store and shl on ↵Nadav Rotem
v2i64; CellSPU/shift_ops.ll fails when promoting elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when ↵Nadav Rotem
promoting elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15SmallVector -> arrayBenjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Mark tADDrSPi as having side effects again.Jakob Stoklund Olesen
It really doesn't, but when r141929 removed the hasSideEffects flag from this instruction, it caused miscompilations. I am guessing that it got moved across a stack pointer update. Also clear isRematerializable after checking that this instruction is in fact never rematerialized in the nightly test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Thumb1 does not support dynamic stack realignment.Chad Rosier
rdar://10288916 is tracking this fix. In the past, instcombine and other passes were promoting alloca alignment past the natural alignment, resulting in dynamic stack realignment. Lang's work now prevents this from happening (LLVM commit r141599). Now that this really shouldn't happen report a fatal error rather than silently generate bad code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-15Mark registers as DEAD because they're really just clobbers.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Add missing correctness check to ARMTargetLowering::ReconstructShuffle. ↵Eli Friedman
Fixes PR11129. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Make sure that the register is in the register class before adding it as a ↵Bill Wendling
machine op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Mark the invoke call instruction as implicitly defining the callee-saved ↵Bill Wendling
registers. The callee-saved registers cannot be live across an invoke call because the control flow may continue along the exceptional edge. When this happens, all of the callee-saved registers are no longer valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Fix a non-firing assert. Change:Richard Trieu
assert("bad SymbolicOp.VariantKind"); To: assert(0 && "bad SymbolicOp.VariantKind"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14A few 80-col violations.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141988 91177308-0d34-0410-b5e6-96231b3b80d8
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