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2013-02-15Remove a final dependency on the form field in tablegen; which is a remnantReed Kotler
of the old jit and which we don't intend to support in mips16 or micromips. This dependency is for the testing of whether an instruction is a pseudo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Hexagon: Set appropriate TSFlags to the loads/stores with global address toJyotsna Verma
support constant extension. This patch doesn't introduce any functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15AArch64: add branch fixup pass.Tim Northover
This is essentially a stripped-down version of the ConstandIslands pass (which always had these two functions), providing just the features necessary for correctness. In particular there needs to be a way to resolve the situation where a conditional branch's destination block ends up out of range. This issue crops up when self-hosting for AArch64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Give these callbacks hidden visibility. It is better to not export them moreRafael Espindola
than we need to and some ELF linkers complain about directly accessing symbols with default visibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Don't make assumptions about the mangling of static functions in extern "C"Rafael Espindola
blocks. We still don't have consensus if we should try to change clang or the standard, but llvm should work with compilers that implement the current standard and mangle those functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Make helpers static. Add missing include so LLVMInitializeObjCARCOpts gets C ↵Benjamin Kramer
linkage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover
This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15AArch64: refactor frame handling to use movz/movk for overlarge offsets.Tim Northover
In the near future litpools will be in a different section, which means that any access to them is at least two instructions. This makes the case for a movz/movk pair (if total offset <= 32-bits) even more compelling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler
not matter but makes it more gcc compatible which avoids possible subtle problems. Also, turned back on a disabled check in helloworld.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14[mips] Disallow moving load/store instructions past volatile instructions.Akira Hatanaka
Unfortunately, I wasn't able to create a test case that demonstrates the problem I was trying to fix with this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14[mips] Replace usage of SmallSet with BitVector, which is used to keep track ofAkira Hatanaka
defined and used registers. Also add a few helper functions to simplify the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14[mips] Fix comments and coding style violations. Declare functions to be const.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14The ARM NEON vector compare instructions take three arguments. However, the Joel Jones
assembler should also accept a two arg form, as the docuemntation specifies that the first (destination) register is optional. This patch uses TwoOperandAliasConstraint to add the two argument form. It also fixes an 80-column formatting problem in: test/MC/ARM/neon-bitwise-encoding <rdar://problem/12909419> Clang rejects ARM NEON assembly instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175221 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14The operand listing is very much outdated.Eli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14[mips] Simplify code in function Filler::findDelayInstr.Akira Hatanaka
1. Define and use function terminateSearch. 2. Use MachineBasicBlock::iterator instead of MachineBasicBlock::instr_iterator. 3. Delete the line which checks whether an instruction is a pseudo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Simplify code. Remove "else after return".Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175212 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Hexagon: Change insn class to support instruction encoding.Jyotsna Verma
This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14added basic support for Intel ADX instructionsKay Tiong Khoo
-feature flag, instructions definitions, test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600/SI: Fix int_SI_fs_interp_constantMichel Danzer
The important fix is that the constant interpolation value is stored in the parameter slot P0, which is encoded as 2. In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and add a special operand class for the parameter slots for type checking and pretty printing. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-1480-colNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma
This patch doesn't introduce any functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175187 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao
inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune
It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175183 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Export instructions are no longer terminatorVincent Lejeune
This allows MachineInstScheduler to reorder them, and thus make scheduling more efficient. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175182 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Fold zero/one in export instructionsVincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600: Do not fold modifier/litterals in vector instVincent Lejeune
This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14AArch64: switch from neverHasSideEffects to hasSideEffects.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14AArch64: stop claiming that NEON registers are usable for now.Tim Northover
If vector types have legal register classes, then LLVM bypasses LegalizeTypes on them, which causes faults currently since the code to handle them isn't in place. This fixes test failures when AArch64 is the default target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175172 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14AArch64: add block comments where missingTim Northover
Only comments affected. No code change at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky
Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStackMichel Danzer
Fixes assertion failure in newly added lit test. Might just be a bandaid that needs to be revisited. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175139 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Revert r175120 and r175121. Clang is producing the expected asm names again.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Remove the form field from Mips16 instruction formats and set thingsReed Kotler
up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Don't assume the mangling of static functions.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Don't asume that a static function in an extern "C" block will not be mangled.Rafael Espindola
Since functions with internal linkage don't have language linkage, it is valid to overload them: extern "C" { static int foo(); static int foo(int); } So we mangle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13temporarily revert the patch due to some conflictsWeiming Zhao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13R600: Add support for 128-bit parametersTom Stellard
NOTE: This is a candidate for the Mesa stable branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Don't build tail calls to functions with three inreg arguments on x86-32 PIC.Nick Lewycky
Fixes PR15250! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175092 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Bug fix 13622: Add paired register support for inline asm with 64-bit data ↵Weiming Zhao
on ARM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma
instead of redefining separate instructions for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13[ms-inline-asm] Add support for memory references that have non-immediateChad Rosier
displacements. rdar://12974533 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler
if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Add registration for PPC-specific passes to allow the IR to be dumpedKrzysztof Parzyszek
via -print-after-all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer
This happens when there is both stack realignment and a dynamic alloca in the function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the base pointer and the next register spill will write into oblivion. Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas and freebsd a 4 byte stack alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175057 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Make jumptables work for -staticReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175044 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky
since a caller uses preserved registers across the call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher
assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175036 91177308-0d34-0410-b5e6-96231b3b80d8
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