| Age | Commit message (Expand) | Author |
|---|
| 2013-03-28 | Add the Haswell machine model. | Nadav Rotem |
| 2013-03-28 | Remove the unused port from the SandyBridge machine model | Nadav Rotem |
| 2013-03-28 | Add ADX CPUID detection | Michael Liao |
| 2013-03-28 | These two are default in the constructor for MCAsmInfo. | Eric Christopher |
| 2013-03-28 | Make Win32 put the SRet address into EAX, fixes PR15556 | Timur Iskhodzhanov |
| 2013-03-28 | Only enable 64-bit bswap DAG combines for PPC64 | Hal Finkel |
| 2013-03-28 | Hexagon: Replace switch-case in isDotNewInst with TSFlags. | Jyotsna Verma |
| 2013-03-28 | Fix bad indentation in r178276 | Hal Finkel |
| 2013-03-28 | Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. | Jyotsna Verma |
| 2013-03-28 | Use direct types in most PowerPC Altivec instructions and patterns. | Bill Schmidt |
| 2013-03-28 | Add the PPC64 ldbrx/stdbrx instructions | Hal Finkel |
| 2013-03-28 | Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when th... | Gordon Keiser |
| 2013-03-28 | Testing commit access to llvm. Remove two lines of whitespace from the Thumb... | Gordon Keiser |
| 2013-03-28 | Hexagon: Use multiclass for gp-relative instructions. | Jyotsna Verma |
| 2013-03-28 | AArch64: implement GICv3 system registers | Tim Northover |
| 2013-03-28 | Add the PPC64 popcntd instruction | Hal Finkel |
| 2013-03-28 | Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructions | Hal Finkel |
| 2013-03-28 | Fix typo in PPCInstr64Bit | Hal Finkel |
| 2013-03-27 | This patch follows is a follow up to r178171, which uses the register | Preston Gurd |
| 2013-03-27 | [ms-inline asm] Add support of imm displacement before bracketed memory | Chad Rosier |
| 2013-03-27 | Resynchronize isLoadFromStackSlot with LoadRegFromStackSlot (and stores) in P... | Hal Finkel |
| 2013-03-27 | For the current Atom processor, the fastest way to handle a call | Preston Gurd |
| 2013-03-27 | Fix typo (common to both X86 and PPC) | Hal Finkel |
| 2013-03-27 | Remove more dead LR-as-GPR PPC code | Hal Finkel |
| 2013-03-27 | Remove "gpr0 allocation" from the PPC README TODO list | Hal Finkel |
| 2013-03-27 | R600/SI: add SETO/SETUO patterns | Christian Konig |
| 2013-03-27 | Print PPC ZERO as 0 (not r0) even on Darwin | Hal Finkel |
| 2013-03-27 | Switch to LLVM support function abs64 to keep VS2008 happy. | Tim Northover |
| 2013-03-27 | Enabling the generation of dependency breakers for partial updates on Cortex-... | Silviu Baranga |
| 2013-03-27 | Hexagon: Disable optimizations at O0. | Jyotsna Verma |
| 2013-03-27 | R600/SI: add cummuting of rev instructions | Christian Konig |
| 2013-03-27 | R600/SI: add mulhu/mulhs patterns | Christian Konig |
| 2013-03-27 | R600/SI: add srl/sha patterns for SI | Christian Konig |
| 2013-03-27 | Allocate r0 on PPC | Hal Finkel |
| 2013-03-27 | Use the PPC no-r0 class on the TOC LD pseudos | Hal Finkel |
| 2013-03-27 | Apply the no-r0 register class to the PPC SELECT_CC_I[4|8] pseudos | Hal Finkel |
| 2013-03-27 | Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructions | Hal Finkel |
| 2013-03-27 | Remove the link register from the GPR classes on PowerPC. | Bill Schmidt |
| 2013-03-27 | Don't spill PPC VRSAVE on non-Darwin (even in SjLj) | Hal Finkel |
| 2013-03-26 | Add XTEST codegen support | Michael Liao |
| 2013-03-26 | Add HLE target feature | Michael Liao |
| 2013-03-26 | Enable SandyBridgeModel for all modern Intel P6 descendants. | Jakob Stoklund Olesen |
| 2013-03-26 | Restore real bit lengths on PPC register numbers | Hal Finkel |
| 2013-03-26 | PPC: Use HWEncoding and TRI->getEncodingValue | Hal Finkel |
| 2013-03-26 | R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. [-Wu... | NAKAMURA Takumi |
| 2013-03-26 | Use multiple virtual registers in PPC CR spilling | Hal Finkel |
| 2013-03-26 | Update PPCRegisterInfo's use of virtual registers to be SSA | Hal Finkel |
| 2013-03-26 | Annotate the remaining x86 instructions with SchedRW lists. | Jakob Stoklund Olesen |
| 2013-03-26 | Annotate x87 and mmx instructions with SchedRW lists. | Jakob Stoklund Olesen |
| 2013-03-26 | Annotate control instructions with SchedRW lists. | Jakob Stoklund Olesen |
