| Age | Commit message (Expand) | Author |
|---|
| 2013-03-26 | Annotate the rest of X86InstrInfo.td with SchedRW lists. | Jakob Stoklund Olesen |
| 2013-03-26 | Add PREFETCHW codegen support | Michael Liao |
| 2013-03-26 | Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. | Jyotsna Verma |
| 2013-03-26 | Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/... | Jyotsna Verma |
| 2013-03-26 | Revert ARM Scheduler Model: Add resources instructions, map resources | Arnold Schwaighofer |
| 2013-03-26 | Remove default case from fully covered switch. | Benjamin Kramer |
| 2013-03-26 | R600/SI: improve post ISel folding | Christian Konig |
| 2013-03-26 | R600/SI: improve vector interpolation | Christian Konig |
| 2013-03-26 | R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLE | Christian Konig |
| 2013-03-26 | R600/SI: switch back to RegPressure scheduling | Christian Konig |
| 2013-03-26 | R600/SI: mark most intrinsics as readnone v2 | Christian Konig |
| 2013-03-26 | R600/SI: replace WQM intrinsic | Christian Konig |
| 2013-03-26 | R600/SI: fix ELSE pseudo op handling | Christian Konig |
| 2013-03-26 | Patch by Gordon Keiser! | Joe Abbey |
| 2013-03-26 | PowerPC: Mark patterns as isCodeGenOnly. | Ulrich Weigand |
| 2013-03-26 | PowerPC: Simplify handling of fixups. | Ulrich Weigand |
| 2013-03-26 | PowerPC: Simplify FADD in round-to-zero mode. | Ulrich Weigand |
| 2013-03-26 | PowerPC: Remove LDrs pattern. | Ulrich Weigand |
| 2013-03-26 | PowerPC: Remove ADDIL patterns. | Ulrich Weigand |
| 2013-03-26 | PowerPC: Use CCBITRC operand for ISEL patterns. | Ulrich Weigand |
| 2013-03-26 | PowerPC: Simplify BLR pattern. | Ulrich Weigand |
| 2013-03-26 | PowerPC: Move some 64-bit branch patterns. | Ulrich Weigand |
| 2013-03-26 | R600: fix DenseMap with pointer key iteration in the structurizer | Christian Konig |
| 2013-03-26 | ARM Scheduler Model: Add resources instructions, map resources in subtargets | Arnold Schwaighofer |
| 2013-03-26 | ARM Scheduler Model: Partial implementation of the new machine scheduler model | Arnold Schwaighofer |
| 2013-03-25 | Revise alignment checking/calculation on 256-bit unaligned memory access | Michael Liao |
| 2013-03-25 | Add a scheduling model for Intel Sandy Bridge microarchitecture. | Jakob Stoklund Olesen |
| 2013-03-25 | Remove IIC_DEFAULT from X86Schedule.td | Jakob Stoklund Olesen |
| 2013-03-25 | Annotate X86InstrCompiler.td with SchedRW lists. | Jakob Stoklund Olesen |
| 2013-03-25 | Annotate shifts and rotates with SchedRW lists. | Jakob Stoklund Olesen |
| 2013-03-25 | X86DisassemblerDecoder.c: Make this C89-compliant. | NAKAMURA Takumi |
| 2013-03-25 | Whitespace. | NAKAMURA Takumi |
| 2013-03-25 | Fix comment. | Akira Hatanaka |
| 2013-03-25 | Use direct types in PowerPC instruction patterns. | Ulrich Weigand |
| 2013-03-25 | Use direct types in PowerPC Pat patterns. | Ulrich Weigand |
| 2013-03-25 | x86 -- add the XTEST instruction | Dave Zarzycki |
| 2013-03-25 | x86 -- disassemble the REP/REPNE prefix when needed | Dave Zarzycki |
| 2013-03-25 | Remove assert. There may be target-dependent attributes left. | Bill Wendling |
| 2013-03-25 | [arm load/store optimizer] When trying to merge a base update load/store, make | Chad Rosier |
| 2013-03-24 | [NVPTX] Fix handling of vector arguments | Justin Holewinski |
| 2013-03-24 | Clean up Sparc patterns. | Jakob Stoklund Olesen |
| 2013-03-24 | Give Sparc instruction patterns direct types instead of register classes. | Jakob Stoklund Olesen |
| 2013-03-23 | PPC ZERO register needs a register number of 0. | Hal Finkel |
| 2013-03-23 | Note in PPCFunctionInfo VRSAVE spills | Hal Finkel |
| 2013-03-23 | MCize the bcl instruction in PPCAsmPrinter | Hal Finkel |
| 2013-03-23 | Use direct types in Sparc def : Pat patterns. | Jakob Stoklund Olesen |
| 2013-03-23 | Cleanup some unused reg. scavenger parameters in PPCRegisterInfo | Hal Finkel |
| 2013-03-23 | Remove dead PPC LR spilling code | Hal Finkel |
| 2013-03-22 | Allow the register scavenger to spill multiple registers | Hal Finkel |
| 2013-03-22 | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma |
