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2012-06-25Add SSE2 predicate to CVTPS2PD instructions. Doesn't matter much because ↵Craig Topper
there are no patterns in the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-25Remove codegen only instruction in favor of one that has the same ↵Craig Topper
definition. Make some pattern operands more explicit about types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159126 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24%RCX is not a function live-out in eh.return functions.Jakob Stoklund Olesen
The function live-out registers must be live at all function returns, and %RCX is only used by eh.return. When a function also has a normal return, only %RAX holds a return value. This fixes PR13188. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159112 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with ↵Craig Topper
patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove intrinsic specific instructions for (V)CVTPS2DQ and replace with ↵Craig Topper
patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159108 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Fix build failures from r159106.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove intrinsic specific instructions for CVTPD2PS and replace with just ↵Craig Topper
patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159106 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove intrinsic specific instructions for CVTPD2DQ. Replace with patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24Remove code i'd been testing with but didn't mean to commit. OopsPete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24DAG legalisation can now handle illegal fma vector types by scalarisationPete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Remove intrinsic specific instructions for (V)CVTDQ2PS. Use a Pat instead ↵Craig Topper
instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional ↵Craig Topper
change because there are no patterns in the instructions. Also fix a typo in a comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to ↵Craig Topper
the SSE2 section of the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Add a microoptimization note.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Extend the IL for selecting TLS models (PR9788)Hans Wennborg
This allows the user/front-end to specify a model that is better than what LLVM would choose by default. For example, a variable might be declared as @x = thread_local(initialexec) global i32 42 if it will not be used in a shared library that is dlopen'ed. If the specified model isn't supported by the target, or if LLVM can make a better choice, a different model may be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Use correct memory types for (V)CVTDQ2PD instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Silence an unused variable warning on release builds.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Compress flags in X86 op folding to reduce space in static tables.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Make helper method static since it doesn't use anything in the class.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Remove intrinsic specific instructions for 128-bit (V)CVTDQ2PD. Replace with ↵Craig Topper
intrinsic patterns. Mem forms omitted because the load size is only 64-bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159070 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Handle aliases to tls variables in all architectures, not just x86.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159058 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23(sub X, imm) gets canonicalized to (add X, -imm)Evan Cheng
There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach
As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159051 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Add support for the PPC isel instruction.Hal Finkel
The isel (integer select) instruction is supported on the 440 and A2 embedded cores and on the POWER7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159035 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Revert r158679 - use case is unclear (and it increases the memory footprint).Hal Finkel
Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Use "NoItineraries" for processors with no itineraries.Andrew Trick
This makes it explicit when ScoreboardHazardRecognizer will be used. "GenericItineraries" would only make sense if it contained real itinerary values and still required ScoreboardHazardRecognizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158963 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Functions calling __builtin_eh_return must have a frame pointer.Jakob Stoklund Olesen
The code in X86TargetLowering::LowerEH_RETURN() assumes that a frame pointer exists, but the frame pointer was forced by the presence of llvm.eh.unwind.init which isn't guaranteed. If llvm.eh.unwind.init is actually required in functions calling eh.return (is it?), we should diagnose that instead of emitting bad machine code. This should fix the dragonegg-x86_64-linux-gcc-4.6-test bot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22ARM scheduling fix: don't guess at implicit operand latency.Andrew Trick
This is a minor drive-by fix with no robust way to unit test. As an example see neon-div.ll: SU(16): %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill> val SU(1): Latency=2 Reg=%Q8 ...should be latency=1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22ARM scheduling fix: compute predicated implicit use properly.Andrew Trick
Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames
boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Convert the PPC backend to use the new FMA infrastructure.Hal Finkel
The existing contraction patterns are replaced with fma/fneg. Overall functionality should be the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-211. fix null program output after some other changesAkira Hatanaka
2. re-enable null.ll test 3. fix some minor style violations Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc ↵Hal Finkel
stores on PPC. Thanks to Tobias von Koch for pointing out this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158932 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21The inline asm operand modifier 'c' is suppose Jack Carter
to be generic across architectures. It has the following description in the gnu sources: Substitute immediate value without immediate syntax Several Architectures such as x86 have local implementations of operand modifier 'c' which go beyond the above description slightly. To make use of the generic modifiers without overriding local implementation one can make a call to the base class method for AsmPrinter::PrintAsmOperand() in the locally derived method's "default" case in the switch statement. That way if it is already defined locally the generic version will never get called. This change is needed when test/CodeGen/generic/asm-large-immediate.ll failed on a native Mips board. The test was assuming a generic implementation was in place. Affected files: lib/Target/Mips/MipsAsmPrinter.cpp: Changed the default case to call the base method. lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'c' to the switch cases. test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158925 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Add a missing llvm.fma -> VFNMS pattern to the ARM backend.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Revert r158846.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20In MipsDisassembler.cpp, instead of defining register class tables, use the onesAkira Hatanaka
that are generated by TableGen and are already available in MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen. Also, fix bug in function DecodeAFGR64RegisterClass. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Remove 'static' from inline functions defined in header files.Chandler Carruth
There is a pretty staggering amount of this in LLVM's header files, this is not all of the instances I'm afraid. These include all of the functions that (in my build) are used by a non-static inline (or external) function. Specifically, these issues were caught by the new '-Winternal-linkage-in-inline' warning. I'll try to just clean up the remainder of the clearly redundant "static inline" cases on functions (not methods!) defined within headers if I can do so in a reliable way. There were even several cases of a missing 'inline' altogether, or my personal favorite "static bool inline". Go figure. ;] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add predicate check around some patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add predicate check around some patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Don't insert 128-bit UNDEF into 256-bit vectors. Just keep the 256-bit ↵Craig Topper
vector. Original patch by Elena Demikhovsky. Tweaked by me to allow possibility of covering more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add DAG-combines for aggressive FMA formation.Lang Hames
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Implement PPCInstrInfo::isCoalescableExtInstr().Jakob Stoklund Olesen
The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Have ARM ELF use correct reloc for "b" instr.Jan Wen Voung
The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Mark most PPC register classes to avoid write-after-write.Hal Finkel
For processors with the G5-like instruction-grouping scheme, this helps avoid early group termination due to a write-after-write dependency within the group. It should also help on pipelined embedded cores. On POWER7, over the test suite, this gives an average 0.5% speedup. The largest speedups are: SingleSource/Benchmarks/Stanford/Quicksort - 33% MultiSource/Applications/d/make_dparser - 21% MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12% MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12% Largest slowdowns: SingleSource/Benchmarks/Stanford/Bubblesort - 23% MultiSource/Benchmarks/Prolangs-C++/city/city - 21% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16% MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Make MipsLongBranch::runOnMachineFunction return true.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158702 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Use MachineBasicBlock::instr_iterator instead of MachineBasicBlock::iterator inAkira Hatanaka
MipsCodeEmitter.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158701 91177308-0d34-0410-b5e6-96231b3b80d8
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