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2012-08-08X86: enable CSE between CMP and SUBManman Ren
We perform the following: 1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering. 2> Modify MachineCSE to correctly handle implicit defs. 3> Convert SUB back to CMP if possible at peephole. Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled by peephole now. rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08Don't scan physreg use-def chains looking for a PIC base.Jakob Stoklund Olesen
We can't rematerialize a PIC base after register allocation anyway, and scanning physreg use-def chains is very expensive in a function with many calls. <rdar://problem/12047515> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07X86 cmp lowering is looking past truncate on the condition node. It should onlyEvan Cheng
do so when the high bits are known zero. This caused a subtle miscompilation. rdar://12027825 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07Add a comment about mftb vs. mfspr on PPC.Hal Finkel
Thanks to Alex Rosenberg for the suggestion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07Revert r161371. Removing the 'const' before Type is a "good thing".Bill Wendling
--- Reverse-merging r161371 into '.': U include/llvm/Target/TargetData.h U lib/Target/TargetData.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161394 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07The define for 64 bit sign extension neglected to Jack Carter
initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161377 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07Constify the Type parameter to some methods (which are const anyway).Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161371 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.Andrew Trick
This allows codegen passes to query properties like InstrItins->SchedModel->IssueWidth. It also ensure's that computeOperandLatency returns the X86 defaults for loads and "high latency ops". This should have no significant impact on existing schedulers because X86 defaults happen to be the same as global defaults. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07Mips relocation R_MIPS_64 relocates a 64 bit double word.Jack Carter
I hit this in a very large program (spirit.cpp), but have not figured out how to make a small make check test for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 Jack Carter
were using a class defined for 32 bit instructions and thus the instruction was for addiu instead of daddiu. This was corrected by adding the instruction opcode as a field in the base class to be filled in by the defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.Jack Carter
These 2 relocations gain access to the highest and the second highest 16 bits of a 64 bit object. R_MIPS_HIGHER %higher(A+S) The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. R_MIPS_HIGHEST %highest(A+S) The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161348 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06MFTB on PPC64 should really be encoded using MFSPR.Hal Finkel
The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06Add support for the OpenBSD for Bitrig.Eric Christopher
Patch by David Hill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06Remove empty overrides of processFunctionBeforeFrameFinalized().Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires ↵Craig Topper
custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-05Remove custom inserter for MWAIT. It doesn't do anything that couldn't be ↵Craig Topper
represented in a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161306 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-05Use a COPY node instead of an explicit MOVA opcode in the custom insterter ↵Craig Topper
for pcmpestrm/pcmpistrm. Allows the register allocator to handle it better and prevent wasted identity moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Add readcyclecounter lowering on PPC64.Hal Finkel
On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Skip impdef regs during eabi save/restore list emission to workaround PR11902Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack ↵Anton Korobeynikov
stuff (this corresponds by spilling/reloading regs in DTriple / DQuad reg classes). No testcase, found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Add stack spill / reload instructions for DTriple and DQuad register ↵Anton Korobeynikov
classes, which were missed for no reason. This fixes PR13377 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-031. Redo mips16 instructions to avoid multiple opcodes for same instruction.Akira Hatanaka
Change these to patterns. 2. Add another 16 instructions. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161272 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03allow 'make CPPFLAGS=<something>' work againGabor Greif
this makes this hack a bit more bearable for poor souls who need to pass custom preprocessor flags to the build process git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Fall back to selection DAG isel for calls to builtin functions.Bob Wilson
Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Add new getLibFunc method to TargetLibraryInfo.Bob Wilson
This just provides a way to look up a LibFunc::Func enum value for a function name. Alphabetize the enums and function names so we can use a binary search. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161231 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03[arm-fast-isel] Add support for shl, lshr, and ashr.Jush Lu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Add support for the ARM GHC calling convention, this patch was in 3.0,Eric Christopher
but somehow managed to be dropped later. Patch by Karel Gardas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02ARM: Tidy up. Remove unused template parameters.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02ARM: More InstAlias refactors to use #NAME#.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161220 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02ARM: Refactor instaliases using TableGen support for #NAME#.Jim Grosbach
Now that TableGen supports references to NAME w/o it being explicitly referenced in the definition's own name, use that to simplify assembly InstAlias definitions in multiclasses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161218 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Add more comments and use early returns to reduce nesting in isLoadFoldable. Also disable folding for V_SET0 to avoid introducing a const pool entry and a const pool load. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Move the code that creates instances of MipsInstrInfo and MipsFrameLowering outAkira Hatanaka
of MipsTargetMachine.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161191 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Set transient stack alignment in constructor of MipsFrameLowering and re-enableAkira Hatanaka
test o32_cc_vararg.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Support fpv4 for ARM Cortex-M4.Jiangning Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161163 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu
index issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01X86: mark GATHER instructios as mayLoadManman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01ARM: Remove redundant instalias.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Clean up formatting.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161133 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Tidy up.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Added FMA functionality to X86 target.Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper
used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Implement MipsJITInfo::replaceMachineCodeForFunction.Akira Hatanaka
No new test case is added. This patch makes test JITTest.FunctionIsRecompiledAndRelinked pass on mips platform. Patch by Petar Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161098 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Remove unused variable.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emitsAkira Hatanaka
instructions that decrement and increment the stack pointer before and after a call when the function does not have a reserved call frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka
MipsSERegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering andAkira Hatanaka
MipsSEFrameLowering. Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be reserved if there is a call with a large call frame or there are variable sized objects on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161090 91177308-0d34-0410-b5e6-96231b3b80d8
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