aboutsummaryrefslogtreecommitdiff
path: root/lib/Target
AgeCommit message (Collapse)Author
2012-08-16Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.Anitha Boyapati
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162012 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162010 ↵Anitha Boyapati
91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16Add Android ABI to Mips backend to handle functions returning vectors of fourAkira Hatanaka
floats. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162008 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen
The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng
unaligned access. rdar://12091029 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161962 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen
When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14The names of VFP variants of half-to-float conversion instructions wereAnton Korobeynikov
reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14This needs braces. Spotted by Bill.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161906 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14minor fix of X86ISD::VSEXT_MOVL dumpMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14fix PR11334Michael Liao
- FP_EXTEND only support extending from vectors with matching elements. This results in the scalarization of extending to v2f64 from v2f32, which will be legalized to v4f32 not matching with v2f64. - add X86-specific VFPEXT supproting extending from v4f32 to v2f64. - add BUILD_VECTOR lowering helper to recover back the original extending from v4f32 to v2f64. - test case is enhanced to include different vector width. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161894 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14Switch the fixed-length disassembler to be table-driven.Jim Grosbach
Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14Factor duplicate calls to getUNDEF in several functions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161860 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14Re-factor intrinsic lowering to combine common parts of similar intrinsics. ↵Craig Topper
Reduces compiled code size a little bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Remove the TII::scheduleTwoAddrSource() hook.Jakob Stoklund Olesen
It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13ARM: enable struct byval for AAPCS-VFP.Manman Ren
This change is to be enabled in clang. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161789 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13[Hexagon] Don't mark callee saved registers as clobbered by a tail callArnold Schwaighofer
This was causing unnecessary spills/restores of callee saved registers. Fixes PR13572. Patch by Pranav Bhandarkar! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ↵Nadav Rotem
ISDNode has more than one user. rdar://11876519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr fromManman Ren
OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Add support for the %H output modifier.Eric Christopher
Patch by Weiming Zhao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13X86: when auto-detecting the subtarget features, make sure use IsIntel to detectManman Ren
Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161763 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Use correct loads for vector types during extending-load operations.Tim Northover
Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit accesses being selected, so we need to use an appropriate width load in those cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and ↵Craig Topper
putting an a couple if conditions in a better order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161746 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Refactor code a bit to share commonalities. No functional change intended.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Fix an unused variable warning from r161742.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Remove the LowerMMXCONCAT_VECTORS function. It could never execute because ↵Craig Topper
there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Remove call to setOperationAction for SETCC of v4f32. SETCC returns an ↵Craig Topper
integer type not an FP type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Remove unnecessary call to setOperationAction for SETCC of v2i64 under ↵Craig Topper
SSE42. It was already called for the same under SSE2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer
architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161736 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Change addTypeForNeon to use MVT instead of EVT so all the calls to ↵Craig Topper
getSimpleVT can be removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Make replace many calls to getSizeInBits() with is128BitVector/is256BitVectorCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Use MVT.isXBitVector instead of EVT.isXBitVector when setting up operation ↵Craig Topper
actions. Compiles to smaller code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11fix PR13577, an issue introduced by r161687Michael Liao
- FCMOV only supports a subset of X86 conditions. Skip boolean simplification if X86 condition is not valid for FCMOV. - add a minimal test case for PR13577. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161732 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11Move setOperationAction for CONCAT_VECTORS for 256-bit vectors into loop ↵Craig Topper
since all 256-bit types are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11Tidy up indentation. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11Fix a cast that was casting away 'const' unnecessarily Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11Add a couple default: llvm_unreachable() to some switch statements. Fix a ↵Craig Topper
bad message in an existing llvm_unreachable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10X86: when we are auto-detecting the subtarget features, make sure we turn onManman Ren
FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge. FeatureFastUAMem is already on if we pass in nehalem or westmere as a command argument. rdar: 7252306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10ARM: enable struct byval for AAPCS.Manman Ren
This change is to be enabled in clang. rdar://9877866 PR://13350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161693 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10add X86-specific DAG optimization to simplify boolean testMichael Liao
- if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value generated from X86ISD::SETCC, try to simplify the boolean value generation and checking by reusing the original EFLAGS with proper condition code - add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places consuming EFLAGS part of patches fixing PR12312 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10remove tailing whitespaces and test commitMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10Add some missing includes for the build against stdcxx.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09Remove getARMRegisterNumbering and replace with calls intoEric Christopher
the register info for getEncodingValue. This builds on the small patch of yesterday to set HWEncoding in the register file. One (deprecated) use was turned into a hard number to avoid needing register info in the old JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09Don't modify MO while use_iterator is still pointing to it.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09[ms-inline asm] Extend the MC AsmParser API to match MCInsts (but not emit).Chad Rosier
This new API will be used by clang to parse ms-style inline asms. One goal of this project is to use this style of inline asm for targets other then x86. Therefore, this API needs to be implemented for non-x86 targets at some point in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161624 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09Another 32 to 64 bit sign extension bug.Jack Carter
The fields in the td definition were switched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer
This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161581 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09This field isn't used anymore, use it with HWEncoding instead.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161564 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08Don't use getNextOperandForReg().Jakob Stoklund Olesen
This way of using getNextOperandForReg() was unlikely to work as intended. We don't give any guarantees about the order of operands in the use-def chains, so looking only at operands following a given operand in the chain doesn't make sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08Added MispredictPenalty to SchedMachineModel.Andrew Trick
This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161469 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-18 16:30:33 +0000