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2012-08-28Explicitly update the number of nodes to be traversedMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Some instructions are passed to the assembler to beJack Carter
transformed to the final instruction variant. An example would be dsrll which is transformed into dsll32 if the shift value is greater than 32. For direct object output we need to do this transformation in the codegen. If the instruction was inside branch delay slot, it was being missed. This patch corrects this oversight. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Emit word of zeroes after the last instruction as a start of the mandatoryRoman Divacky
traceback table on PowerPC64. This helps gdb handle exceptions. The other mandatory fields are ignored by gdb and harder to implement so just add there a FIXME. Patch by Bill Schmidt. PR13641. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Follow-up patch to r162731.Akira Hatanaka
Fix a couple of bugs in mips' long branch pass. This patch was supposed to be committed along with r162731, so I don't have a new test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28The commutative flag is already correctly set within the multiclass. If we setBill Wendling
it here, then a 'register-memory' version would wrongly get the commutative flag. <rdar://problem/12180135> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Fix PR12312Michael Liao
- Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen
ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Fix mips' long branch pass.Akira Hatanaka
Instructions emitted to compute branch offsets now use immediate operands instead of symbolic labels. This change was needed because there were problems when R_MIPS_HI16/LO16 relocations were used to make shared objects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162731 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Split several PPC instruction classes.Hal Finkel
Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Allow remat of LI on PPC.Hal Finkel
Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Eliminate redundant CR moves on PPC32.Hal Finkel
The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Optimize zext on PPC64.Hal Finkel
The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28More missing mayLoad flags on AVX multiclasses.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen
It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Make sure we add the predicate after all of the registers are added.Bill Wendling
<rdar://problem/12183003> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Remove MMX shift intrinsic handling code that also exists in ↵Craig Topper
SelectionDAGBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Don't allow vextractf128 to be folded with unaligned stores. We don't fold ↵Craig Topper
unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Fold some patterns into instruction definitons so tablegen can infer flags ↵Craig Topper
removing the need for an explicit 'neverHasSideEffects = 1' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Add HasAVX1Only predicate and use it for patterns that have an AVX1 ↵Craig Topper
instruction and an AVX2 instruction rather than relying on AddedComplexity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith
Reviewed offline by chandlerc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Add missing mayLoad flags to a large class of AVX *_Int instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Missed tLEApcrelJT.Jakob Stoklund Olesen
ARMConstantIslandPass expects this instruction to stay in the same basic block as the jump table branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Explicitly mark LEApcrel pseudos with hasSideEffects.Jakob Stoklund Olesen
It's not clear that they should be marked as such, but tbb formation fails if t2LEApcrelJT is hoisted of of a loop. This doesn't change the flags on these instructions, UnmodeledSideEffects was already inferred from the missing pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Fix call instruction operands in ARMFastISel.Jakob Stoklund Olesen
The ARM BL and BLX instructions don't have predicate operands, but the thumb variants tBL and tBLX do. The argument registers should be added as implicit uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Mark X86::RET and RETI instructions as variadic.Jakob Stoklund Olesen
There is special magic happening when returning floating point values on the x87 stack. The RET instructions get extra f80 operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Disable Mips' delay slot filler when optimization level is O0.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if itsAkira Hatanaka
second operand is MipsISD::GPRel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162584 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky
In collaboration with Adhemerval Zanella. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162562 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Fix load/store SDNode flags.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162558 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Add missing SDNPSideEffect flags.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Remove more mayLoad workarounds.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Custom lower FMA intrinsics to target specific nodes and remove the patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162534 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Fix undefined behavior (negation of INT_MIN) in ARM backend.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Remove some spurious mayLoad = 0 flags.Jakob Stoklund Olesen
They were inserted to silence TableGen's warning about redundant properties. That warning is now gone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162517 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Add missing SDNP properties on the flushw node.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162515 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24X86MemBarrier has unmodeled side effects.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162514 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Preserve operand flags in convertToThreeAddress() by copying operands.Jakob Stoklund Olesen
No test case, this is a generalization of r160260. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Favor FMA3 over FMA4 if both are enabled.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Use a switch statement instead of a bunch of if-else checks and pull out the ↵Craig Topper
common function call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Remove unused private field to silence build warning.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162426 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23Make function loadImmediate a member of MipsSEInstrInfo and change it to returnAkira Hatanaka
the temporary register that was used to load the immediate. Currently, it always returns register $at, but this will change if, in the future, we decide to use another register. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Add a member of type Mips16InstrInfo/MipsSEInstrInfo to classAkira Hatanaka
Mips16RegisterInfo/MipsSERegisterInfo. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162413 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22[ms-inline asm] Avoid a false positive assertionChad Rosier
Assertion failed: (Start.isValid() == End.isValid() && "Start and end should either both be valid or both be invalid!") when parsing inline asm. SMLoc assumes that the first char * in the source is invalid. However, when parsing an inline asm the mnemonic is at this location. I don't want to change SMLoc, so use a trivial workaround. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162381 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Reduce duplicated hash map lookups.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162362 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper
did getFunction()->getName(). Remove includes of Function.h that are no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Don't cache the MBB in the class. Its only used by one function. Change a ↵Craig Topper
for loop over operands to use unsigned instead of int. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Mark a function as static since it doesn't use anything in the class.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162342 91177308-0d34-0410-b5e6-96231b3b80d8
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