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2012-04-01This commit contains a few changes that had to go in together.Nadav Rotem
1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) (and also scalar_to_vector). 2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src). Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B)) 3. Optimize swizzles of shuffles: shuff(shuff(x, y), undef) -> shuff(x, y). 4. Fix an X86ISelLowering optimization which was very bitcast-sensitive. Code which was previously compiled to this: movd (%rsi), %xmm0 movdqa .LCPI0_0(%rip), %xmm2 pshufb %xmm2, %xmm0 movd (%rdi), %xmm1 pshufb %xmm2, %xmm1 pxor %xmm0, %xmm1 pshufb .LCPI0_1(%rip), %xmm1 movd %xmm1, (%rdi) ret Now compiles to this: movl (%rsi), %eax xorl %eax, (%rdi) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01Set the default PPC node scheduling preference to ILP (for the embedded cores).Hal Finkel
The 440 and A2 cores have detailed itineraries, and this allows them to be fully used to maximize throughput. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01Add ppc440 itin. entries for LdStSTD*Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores.Hal Finkel
Post-RA scheduling gives a significant performance improvement on the embedded cores, so turn it on. Using full anti-dep. breaking is important for FP-intensive blocks, so turn it on (just on the embedded cores for now; this should also be good on the 970s because post-ra scheduling is all that we have for now, but that should have more testing first). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01Add instruction itinerary for the PPC64 A2 core.Hal Finkel
This adds a full itinerary for IBM's PPC64 A2 embedded core. These cores form the basis for the CPUs in the new IBM BG/Q supercomputer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-01Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.Hal Finkel
Loads and stores can have different pipeline behavior, especially on embedded chips. This change allows those differences to be expressed. Except for the 440 scheduler, there are no functionality changes. On the 440, the latency adjustment is only by one cycle, and so this probably does not affect much. Nevertheless, it will make a larger difference in the future and this removes a FIXME from the 440 itin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Fix dynamic linking on PPC64.Hal Finkel
Dynamic linking on PPC64 has had problems since we had to move the top-down hazard-detection logic post-ra. For dynamic linking to work there needs to be a nop placed after every call. It turns out that it is really hard to guarantee that nothing will be placed in between the call (bl) and the nop during post-ra scheduling. Previous attempts at fixing this by placing logic inside the hazard detector only partially worked. This is now fixed in a different way: call+nop codegen-only instructions. As far as CodeGen is concerned the pair is now a single instruction and cannot be split. This solution works much better than previous attempts. The scoreboard hazard detector is also renamed to be more generic, there is currently no cpu-specific logic in it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Select static relocation model if it is jitting.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Add a 2 byte safety margin in offset computations.Jakob Stoklund Olesen
ARMConstantIslandPass still has bugs where jump table compression can cause constant pool entries to go out of range. Add a safety margin of 2 bytes when placing constant islands, but use the real max displacement for verification. <rdar://problem/11156595> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153789 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Add more debugging output to ARMConstantIslandPass.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153788 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Rip out emission of the regIsInRegClass function for the asm printer.Benjamin Kramer
It's slow, bloated and completely redundant with MCRegisterClass::contains. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM fix encoding fixup resolution for ldrd and friends.Jim Grosbach
The 8-bit payload is not contiguous in the opcode. Move the upper nibble over 4 bits into the correct place. rdar://11158641 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM encoding for VSWP got the second operand incorrect.Jim Grosbach
Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM can only use narrow encoding for low regs.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach
Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Add a note about a missed cmov -> sbb opportunity.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy
fixup_arm_condbranch. Patch by Tim Northover! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM target should allow codegenprep to duplicate ret instructions to enable ↵Evan Cheng
tailcall opt. rdar://11140249 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Invalidate liveness in ARMConstantIslandPass.Jakob Stoklund Olesen
This pass splits basic blocks to insert constant islands, and it doesn't recompute the live-in lists. No later passes depend on accurate liveness information. This fixes PR12410 where the machine code verifier was complaining. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153700 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Prefer even-odd D-register pairs.Jakob Stoklund Olesen
We are sometimes allocatinog from the DPair register class which contains odd-even pairs in addition to the Q registers. Place the Q registers first in the DPair allocation order as they can be copied with a single instruction. The odd-even pairs should only be allocated as a last resort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Try using vmov.i32 to materialize FP32 constants that can't be materialized byLang Hames
vmov.f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach
The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Handle register copies for the new ARM register classes.Jakob Stoklund Olesen
ARM recently gained DPair, DTriple, and DQuad register classes. Update copyPhysReg() to handle copies in these register classes. No test case, it is difficult to make the register allocator emit the odd copies reliably. The missing DPair copy caused a failure on partialsums in the nightly test suite. <rdar://problem/11147997> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in ↵Lang Hames
64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Expand FREM.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153671 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Replace assert(0) with llvm_unreachable to avoid warnings about dropping off ↵Benjamin Kramer
the end of a non-void function in Release builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153643 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used ↵Craig Topper
with 'v' version of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153636 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29For X86, change load/dec-or-inc/store into dec-or-inc, respectively.Joel Jones
This is a code change to add support for changing instruction sequences of the form: load inc/dec of 8/16/32/64 bits store into the appropriate X86 inc/dec through memory instruction: inc[qlwb] / dec[qlwb] The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153635 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Reverted to revision 153616 to unblock buildJoel Jones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29For X86, change load/dec-or-inc/store into dec-or-inc, respectively.Joel Jones
This is a code change to add support for changing instruction sequences of the form: load inc/dec of 8/16/32/64 bits store into the appropriate X86 inc/dec through memory instruction: inc[qlwb] / dec[qlwb] The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Enable machine code verification in the entire code generator.Jakob Stoklund Olesen
Some targets still mess up the liveness information, but that isn't verified after MRI->invalidateLiveness(). The verifier can still check other useful things like register classes and CFG, so it should be enabled after all passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Don't kill the base register when expanding strd.Jakob Stoklund Olesen
When an strd instruction doesn't get the registers it wants, it can be expanded into two str instructions. Make sure the first str doesn't kill the base register in the case where the base and data registers are identical: t2STRi12 %R0<kill>, %R0, 4, pred:14, pred:%noreg t2STRi12 %R2<kill>, %R0, 8, pred:14, pred:%noreg <rdar://problem/11101911> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Preserve implicit defs in ARMLoadStoreOptimizer.Jakob Stoklund Olesen
When a number of sub-register VLRDS instructions are combined into a VLDM, preserve any super-register implicit defs. This is required to keep the register scavenger and machine code verifier happy. Enable machine code verification after ARMLoadStoreOptimizer. ARM/2012-01-26-CopyPropKills.ll was failing because of this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Spill DPair registers, not just QPR.Jakob Stoklund Olesen
The arm_neon intrinsics can create virtual registers from the DPair register class which allows both even-odd and odd-even D-register pairs. This fixes PR12389. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Revert r153516: "Invalidate liveness in Thumb2ITBlockPass."Jakob Stoklund Olesen
Revert r153519: "ARMLoadStoreOptimizer invalidates register liveness." These patches caused miscompilations in povray by turning off branch folding's updating of live-in lists. It turns out the the late scheduler depends on the live-in lists, even if it doesn't need correct kill flags. <rdar://problem/11139228> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Add another note about a missed compare with nsw arithmetic instcombine.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.Richard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Turn off post-RA scheduler by default.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Turn on post register allocation scheduler.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153554 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Sort relocation entries before they are written out to a file. MIPS ABIAkira Hatanaka
imposes a constraint that GOT16 referring to a local symbol or HI16 has to be followed immediately by a matching LO16 relocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Emit all directives except for ".cprestore" during asm printing rather than emitAkira Hatanaka
them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153552 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Mark flag neverHasSideEffects of pattern-less instructions that do not haveAkira Hatanaka
any side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Add a note about a cute little fabs optimization.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Add two missed instcombines related to compares with nsw arithmetic.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Remove trailing white space.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Add member EmitNOAT and its setter and getter functions to class ↵Akira Hatanaka
MipsFunctionInfo. If EmitNOAT is true, directives ".set noat" and ".set at" are emitted at the beginning and end of a function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27ARMLoadStoreOptimizer invalidates register liveness.Jakob Stoklund Olesen
This pass tries to update kill flags, but there are still many bugs. Passes after the load/store optimizer don't need accurate liveness, so don't even try. <rdar://problem/11101911> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Invalidate liveness in Thumb2ITBlockPass.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153516 91177308-0d34-0410-b5e6-96231b3b80d8
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