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2012-06-11Enable MFOCRF generation on the PPC A2 core.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Rename the PPC target feature gpul to mfocrf.Hal Finkel
The PPC target feature gpul (IsGigaProcessor) was only used for one thing: To enable the generation of the MFOCRF instruction. Furthermore, this instruction is available on other PPC cores outside of the G5 line. This feature now corresponds to the HasMFOCRF flag. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Add A2 to the list of PPC CPUs recognized by Linux host CPU-type detection.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158322 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Emit the two-operand form of the PPC mfcr instruction as mfocrf.Hal Finkel
This is necessary on Linux and supported on Darwin, see PR2604. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158315 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Add local CPU detection for Linux PPC.Hal Finkel
This functionality mirrors that available on PPC/Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158314 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Add POWER6 and POWER7 CPU types to the PPC backend.Hal Finkel
No functional change; these will be used by upcoming scheduler enhancements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158313 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Re-enable the CMN instruction.Bill Wendling
We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-10Enable ILP scheduling for all nodes by default on PPC.Hal Finkel
Over the entire test-suite, this has an insignificantly negative average performance impact, but reduces some of the worst slowdowns from the anti-dep. change (r158294). Largest speedups: SingleSource/Benchmarks/Stanford/Quicksort - 28% SingleSource/Benchmarks/Stanford/Towers - 24% SingleSource/Benchmarks/Shootout-C++/matrix - 23% MultiSource/Benchmarks/SciMark2-C/scimark2 - 19% MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15% (matrix and automotive-bitcount were both in the top-5 slowdown list from the anti-dep. change) Largest slowdowns: MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28% MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26% MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21% SingleSource/Benchmarks/CoyoteBench/lpbench - 20% MultiSource/Applications/d/make_dparser - 16% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-10Use critical anti-dep. breaking on all PPC targets, but also add other ↵Hal Finkel
register classes. Using 'all' instead of 'critical' would be better because it would make it easier to satisfy the bundling constraints, but, as noted in the FIXME, that is currently not possible with the crs. This yields an average 1% speedup over the entire test suite (on Power 7). Largest speedups: SingleSource/Benchmarks/Shootout-C++/moments - 40% MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28% SingleSource/Benchmarks/BenchmarkGame/nsieve-bits - 26% SingleSource/Benchmarks/McGill/misr - 23% MultiSource/Applications/JM/ldecod/ldecod - 22% Largest slowdowns: SingleSource/Benchmarks/Shootout-C++/matrix - -29% SingleSource/Benchmarks/Shootout-C++/ary3 - -22% MultiSource/Benchmarks/BitBench/uuencode/uuencode - -18% SingleSource/Benchmarks/Shootout-C++/ary - -17% MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - -15% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-10Add intrinsics for immediate form of XOP vprot instructions. Use i128mem ↵Craig Topper
instead of f128mem for integer XOP instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-09Improve ext/trunc patterns on PPC64.Hal Finkel
The PPC64 backend had patterns for i32 <-> i64 extensions and truncations that would leave self-moves in the final assembly. Replacing those patterns with ones based on the SUBREG builtins yields better-looking code. Thanks to Jakob and Owen for their suggestions in this matter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158283 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-09Use XOP vpcom intrinsics in patterns instead of a target specific SDNode ↵Craig Topper
type. Remove the custom lowering code that selected the SDNode type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-09Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate ↵Craig Topper
as an argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-09Silence a gcc-4.6 warning: GCC fails to understand that secondReg and cmpOp2 areDuncan Sands
correlated, and thinks that cmpOp2 may be used uninitialized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158263 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-09Enable tail merging on PPC.Hal Finkel
Tail merging had been disabled on PPC because it would disturb bundling decisions made during pre-RA scheduling on the 970 cores. Now, however, all bundling decisions are made during post-RA scheduling, and tail merging is generally beneficial (the average test-suite speedup is insignificantly positive). Largest test-suite speedups: MultiSource/Benchmarks/mediabench/gsm/toast/toast - 30% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 23% SingleSource/Benchmarks/Shootout-C++/ary - 21% SingleSource/Benchmarks/Stanford/Queens - 17% Largest slowdowns: MultiSource/Benchmarks/MiBench/security-sha/security-sha - 24% MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 22% MultiSource/Applications/JM/ldecod/ldecod - 14% MultiSource/Benchmarks/mediabench/g721/g721encode/encode - 9% This is improved by using full (instead of just critical) anti-dependency breaking, but doing so still causes miscompiles and so cannot yet be enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-09Test commitJack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Remove the TODO statement in the PPC README re: CTR loopsHal Finkel
As Chris points out, this can now be removed! TODO: check if the associated section on viterbi's inner loop can also be removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Enable PPC CTR loop formation by default.Hal Finkel
Thanks to Jakob's help, this now causes no new test suite failures! Over the entire test suite, this gives an average 1% speedup. The largest speedups are: SingleSource/Benchmarks/Misc/pi - 108% SingleSource/Benchmarks/CoyoteBench/lpbench - 54% MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50% SingleSource/Benchmarks/Shootout/ary3 - 32% SingleSource/Benchmarks/Shootout-C++/matrix - 30% The largest slowdowns are: MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30% MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25% MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22% MultiSource/Applications/d/make_dparser - -14% SingleSource/Benchmarks/Shootout-C++/ary - -13% In light of these slowdowns, additional profiling work is obviously needed! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158223 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable.Hal Finkel
Marking these classes as non-alocatable allows CTR loop generation to work correctly with the block placement passes, etc. These register classes are currently used only by some unused TCRETURN patterns. In future cleanup, these will be removed. Thanks again to Jakob for suggesting this fix to the CTR loop problem! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158221 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Enable optimization for integer ABS on X86 if Subtarget has CMOV.Manman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158220 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Fix Target->Codegen dependence.Andrew Trick
Bulk move of TargetInstrInfo implementation into TargetInstrInfoImpl. This is dirty because the code isn't part of TargetInstrInfoImpl class, nor should it be, because the methods are not target hooks. However, it's the current mechanism for keeping libTarget useful outside the backend. You'll get a not-so-nice link error if you invoke a TargetInstrInfo method that depends on CodeGen. The TargetInstrInfoImpl class should probably be removed since it doesn't really solve this problem. To really fix this, we probably need separate interfaces for the CodeGen/nonCodeGen sides of TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Disable the PPC CTR-Loops pass by default.Hal Finkel
The pass itself works well, but the something in the Machine* infrastructure does not understand terminators which define registers. Without the ability to use the block-placement pass, etc. this causes performance regressions (and so is turned off by default). Turning off the analysis turns off the problems with the Machine* infrastructure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Fix a bug in the new PPC CTR-Loops pass.Hal Finkel
The code which tests for an induction operation cannot assume that any ADDI instruction will have a register operand because the operand could also be a frame index; for example: %vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-08Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form ↵Hal Finkel
CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07X86: optimize generated code for integer ABSManman Ren
This patch will generate the following for integer ABS: movl %edi, %eax negl %eax cmovll %edi, %eax INSTEAD OF movl %edi, %ecx sarl $31, %ecx leal (%rdi,%rcx), %eax xorl %ecx, %eax There exists a target-independent DAG combine for integer ABS, which converts integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov. This is implemented in PerformXorCombine. rdar://10695237 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Do not optimize the used bits of the x86 vselect condition operand, when the ↵Nadav Rotem
condition operand is a vector of 1-bit predicates. This may happen on MIC devices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07ARM getOperandLatency rewrite.Andrew Trick
Match expectations of the new latency API. Cleanup and make the logic consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Fix ARM getInstrLatency logic to work with the current API.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07PR13046: we can't replace usage of SUB with CMP in the lowering phase.Manman Ren
It will cause assertion failure later on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158160 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Use a base register instead of an index register with the local dynamic model.Rafael Espindola
Fixes pr13048. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158158 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07X86: replace SUB with CMP if possibleManman Ren
This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158126 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Revert r157755.Manman Ren
The commit is intended to fix rdar://11540023. It is implemented as part of peephole optimization. We can actually implement this in the SelectionDAG lowering phase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Round 2 of dead private variable removal.Benjamin Kramer
LLVM is now -Wunused-private-field clean except for - lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields. - gtest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer
There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier
X86. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Correct decoder for T1 conditional B encodingRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Mark several instructions SSE2 instead of SSE3 as they should be.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05misched: API for minimum vs. expected latency.Andrew Trick
Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Fix header file include order in NVPTX backend NV_CONTRIBYuan Lin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158013 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05PPC32 uses R2 as the TLS register. Fix the copy and paste.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158004 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05X86 itinerary properties.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157981 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05ARM itinerary properties.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05misched: Added MultiIssueItineraries.Andrew Trick
This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Revert commit r157966Joel Jones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-04This change handles a another case for generating the bic instruction Joel Jones
when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. <rdar://problem/11481151> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157966 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-04Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node isAkira Hatanaka
inserted after the shift-left-logical node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-04Implement local-exec TLS on PowerPC.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157935 91177308-0d34-0410-b5e6-96231b3b80d8
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