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2012-10-29Minor style fixes for TargetTransformationInfo and TargetTransformImplHans Wennborg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Expand all atomic ops for mips16.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29PPCSubtarget.h: Add explicit braces.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166932 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29PPCSubtarget.h: Whitespace.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166931 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29This patch adds alignment information for long double to the 64-bit PowerPCBill Schmidt
ELF subtarget. The existing logic is used as a fallback to avoid any changes to the Darwin ABI. PPC64 ELF now has two possible data layout strings: one for FreeBSD, which requires 8-byte alignment, and a default string that requires 16-byte alignment. I've added a test for PPC64 Linux to verify the 16-byte alignment. If somebody wants to add a separate test for FreeBSD, that would be great. Note that there is a companion patch to update the alignment information in Clang, which I am committing now as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166928 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Silence a GCC warning about comparing signed and unsigned types.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Calling TLI->getNumRegisters creates a circular dependency when building ↵Nadav Rotem
LLVM using cmake. Get the number of registers by calling getTypeLegalizationCost. PR14199. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166911 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28Implement brind operator for mips16.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166903 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28Remove TargetELFWriterInfo.Rafael Espindola
All the credit goes to Jan Voung for noticing it was dead! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28This patch is for the implementation of mips16 complex pattern addr16.Reed Kotler
Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27[code size][ARM] Emit regular call instructions instead of the move, branch ↵Quentin Colombet
sequence git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Implement MipsHi for mips16Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27[mips] Do not tail-call optimize vararg functions or functions with byvalAkira Hatanaka
arguments. This is rather conservative and should be fixed later to be more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27[mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in theAkira Hatanaka
previous iteration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Use the methods and classes that were added to simplify LowerCall and Akira Hatanaka
LowerFormalArguments in MipsTargetLowering. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Add method MipsTargetLowering::writeVarArgRegs which copies argument registersAkira Hatanaka
of vararg functions back to the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Add method MipsTargetLowering::passByValArg.Akira Hatanaka
This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Add method MipsTargetLowering::copyByValRegs.Akira Hatanaka
This method copies byval arguments passed in registers onto the stack and has the same functionality as existing functions CopyMips64ByValRegs and ReadByValArg which will be deleted later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Add class MipsCC which provides methods used to analyze formal and callAkira Hatanaka
arguments and inquire about calling convention information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Delete MipsFunctionInfo::InArgFIRange. Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Refactor the VectorTargetTransformInfo interface.Nadav Rotem
Add getCostXXX calls for different families of opcodes, such as casts, arithmetic, cmp, etc. Port the LoopVectorizer to the new API. The LoopVectorizer now finds instructions which will remain uniform after vectorization. It uses this information when calculating the cost of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers."Jakob Stoklund Olesen
Keep the integer_insertelement test case, the new coalescer can handle this kind of lane insertion without help from pseudo-instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166835 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Avoid an unused-variable warning when asserts are disabled.Kaelyn Uhrain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26implement mips16 tls global addrReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Add a comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-2680 col.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Remove ARMBaseRegisterInfo::isReservedReg().Jakob Stoklund Olesen
It is just as easy to use MRI::isReserved() now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Add GPRPair Register class to ARM.Jakob Stoklund Olesen
Some instructions in ARM require 2 even-odd paired GPRs. This patch adds support for such register class. Patch by Weiming Zhao! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Remove the canCombineSubRegIndices() target hook.Jakob Stoklund Olesen
The new coalescer can already do all of this, so there is no need to duplicate the efforts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Emit an error for unsupported SIZE and LENGTH directives.Chad Rosier
Part of rdar://12576868 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Add support for the TYPE operator.Chad Rosier
Part of rdar://12576868 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166790 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166780 ↵Reed Kotler
91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Have the target AsmParser create the asmrewrite for the offsetofChad Rosier
operator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Better handling of OpcodeToISD using enum/switch.Renato Golin
Patch by Pasi Parviainen <pasi.parviainen@iki.fi> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26PowerPC: Fix for rldcl/rldicl/rldicr MC emissionAdhemerval Zanella
This patch fixes the rldcl/rldicl/rldicr instruction emission. The issue is the MDForm_1 instruction defines the PowerISA MB field from 'rldicl' with the name MBE, but RLDCL/RLDICL/RLDICR definition uses as 'MB'. It end up by generatint the 'rldicl' enconding at 'lib/Target/PowerPC/PPCGenMCCodeEmitter.inc' to use the fourth argument as the third. The patch changes it by adjusting to use the fourth argument as intended. Fixes PR14180. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Fix CPP backend for method attributes by creating a block where a new ↵Nicolas Geoffray
AttrBuilder is defined for each attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Implement carry for subtract/add for mips16Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Add VectorTargetTransform::getNumberOfParts.Hal Finkel
As discussed on IRC, add VectorTargetTransform::getNumberOfParts to provide a stable interface to the vector legalization splitting factor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26implement large (>16 bit) constant loading.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25[ms-inline asm] Perform field lookups with the dot operator.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25implement mips16 patterns for select nodesReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25[ms-inline asm] Add support for creating AsmRewrites in the target specificChad Rosier
AsmParser logic. To be used/tested in a subsequent commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Minor cleanups.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25[ms-inline asm] Add error handling to the ParseIntelDotOperator() function.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25This patch fixes the MC object emission of 'nop' for external function callsAdhemerval Zanella
and also fixes the R_PPC64_TOC16 and R_PPC64_TOC16_DS relocation offset. The 'nop' is needed so a restore TOC instruction (ld r2,40(r1)) can be placed by the linker to correct restore the TOC of previous function. Current code has two issues: it defines in PPCInstr64Bit.td file a LDinto_toc and LDtoc_restore as a DSForm_1 with DS_RA=0 where it should be DS=2 (the 8 bytes displacement of the TOC saving). It also wrongly emits a MC intruction using an uint32_t value while the PPC::BL8_NOP_ELF and PPC::BLA8_NOP_ELF are both uint64_t (because of the following 'nop'). This patch corrects the remaining ExecutionEngine using MCJIT: ExecutionEngine/2002-12-16-ArgTest.ll ExecutionEngine/2003-05-07-ArgumentTest.ll ExecutionEngine/2005-12-02-TailCallBug.ll ExecutionEngine/hello.ll ExecutionEngine/hello2.ll ExecutionEngine/test-call.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166682 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25This patch addresses a PPC64 ELF issue with passing parameters consisting ofBill Schmidt
structs having size 3, 5, 6, or 7. Such a struct must be passed and received as right-justified within its register or memory slot. The problem is only present for structs that are passed in registers. Previously, as part of a patch handling all structs of size less than 8, I added logic to rotate the incoming register so that the struct was left- justified prior to storing the whole register. This was incorrect because the address of the parameter had already been adjusted earlier to point to the right-adjusted value in the storage slot. Essentially I had accidentally accounted for the right-adjustment twice. In this patch, I removed the incorrect logic and reorganized the code to make the flow clearer. The removal of the rotates changes the expected code generation, so test case structsinregs.ll has been modified to reflect this. I also added a new test case, jaggedstructs.ll, to demonstrate that structs of these sizes can now be properly received and passed. I've built and tested the code on powerpc64-unknown-linux-gnu with no new regressions. I also ran the GCC compatibility test suite and verified that earlier problems with these structs are now resolved, with no new regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Initial TOC support for PowerPC64 object creationAdhemerval Zanella
This patch adds initial PPC64 TOC MC object creation using the small mcmodel (a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC, R_PPC64_TOC16, and R_PPC64_TOC16DS). The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter' is meant to avoid the creation of an unreferenced ".TOC." symbol (used in the .odp creation) as well to set the R_PPC64_TOC relocation target as the temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should not point to any symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166677 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Atom has SIMD instruction set extension up to SSSE3Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Clean up where SlotSize should be used instead of pointer size.Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Implement a basic cost model for vector and scalar instructions. Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166642 91177308-0d34-0410-b5e6-96231b3b80d8
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