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2012-02-03Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate ↵Craig Topper
performs the same calculation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149683 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Remove unnecessary qualification on 256-bit vector handling in ↵Craig Topper
LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick
Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149671 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149668 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Require non-NULL register masks.Jakob Stoklund Olesen
It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Add pseudo-registers for pairs, triples, and quads of D registers.Jakob Stoklund Olesen
NEON loads and stores accept single and double spaced pairs, triples, and quads of D registers. This patch adds new register classes to accurately model those constraints: Dn, Dn+1 Dn, Dn+2 ---------------------- DPair DPairSpc DTriple DTripleSpc DQuad DQuadSpc Also extend the existing QQ and QQQQ register classes to contains all Q pairs and quads instead of just the aligned ones. These new register classes will make it possible to accurately model constraints on NEON loads and stores, and we can get rid of all the NEON pseudo-instructions. The late scheduler will be able to accurately model instruction dependencies from the explicit operands. This more than doubles the number of ARM registers, but the backend passes are quite good at handling this. The llc -O0 compile time only regresses by 1.5%. Future work on register mask operands will recover this regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149640 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Minor change in signature of the getZeroVector() Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Optimization for SIGN_EXTEND operation on AVX.Elena Demikhovsky
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32 extensions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Unbreak the MSVC build.Francois Pichet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Set EFLAGS correctly in EmitLoweredSelect on X86.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149597 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Set the correct stack pointer register.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149585 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer andAkira Hatanaka
selector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149584 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02Add DWARF numbers of 64-bit registers.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149583 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Fix the cmake buildRafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Instruction scheduling itinerary for Intel Atom.Andrew Trick
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Move ARM subreg index compositions to the SubRegIndex itself.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Avoid creating an extract element to an illegal type after LegalizeTypes has ↵Mon P Wang
run. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick
automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Tidy up.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Passing AVX 256-bit structures in Win64 was wrong.Elena Demikhovsky
Fixed Win64 calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Shortened code in shuffle masksElena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149493 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Optimization for "truncate" operation on AVX.Elena Demikhovsky
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01SwitchInst refactoring.Stepan Dyatkovskiy
The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149481 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Don't create VBROADCAST nodes if any nodes use the chain result from the ↵Craig Topper
load. Fixes PR11900. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149478 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-01Revert Chris' commits up to r149348 that started causing VMCoreTests unit ↵Argyrios Kyrtzidis
test to fail. These are: r149348 r149351 r149352 r149354 r149356 r149357 r149361 r149362 r149364 r149365 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Tidy up. One more return type mismatch fix.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149452 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Refactor loop for better readability.Jim Grosbach
Excellent suggestion from Ben Kramer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Add explanatory comment.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Add assembler dialect attribute in asm parser which lets target specific asm ↵Devang Patel
parser change dialect on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31Remove pcmpgt/pcmpeq intrinsics as clang is not using them.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31with recent changes, ConstantArray is never a "string". Remove the associatedChris Lattner
methods and constant fold the clients to false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149362 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31use the right accessor for ConstantDataArray.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149342 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30Intel syntax. Adjust special code, used to recognize cmp<comparison ↵Devang Patel
code>{ss,sd,ps,pd}, for intel syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30Intel syntax. Support .intel_syntax directive.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30Fix refacto.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30Eliminate narrowing conversion in initializer list, to make C++11 happyDouglas Gregor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30X86: Simplify shuffle mask generation code.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30Fix pattern for memory form of PSHUFD for use with FP vectors to remove ↵Craig Topper
bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic ↵Craig Topper
patterns with custom lowering to a target specific nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-29Cleanups for EABI standard functionsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-29Use base AAPCS for varargs functions even for AAPCS-VFP CCAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28Add a note about a potential optimization for clz/ctz patterns for ARMBob Wilson
(and other targets). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149182 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM ↵James Molloy
and MIPS ELF backends. Fixes PR11877 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Move some patterns back near their instructions and use AddedComplexity to ↵Craig Topper
fix priority. Merge some patterns into their instruction definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Keep source location information for X86 MCFixup's.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149106 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27Better user diagnostics for more ARM MachO relocation errors.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149102 91177308-0d34-0410-b5e6-96231b3b80d8
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