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2012-03-05ARM Remove a bit of dead code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach
With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach
Used to allow context sensitive printing of super-register or sub-register references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Address Evan's comments for r151877.Chad Rosier
Specifically, remove the magic number when checking to see if the copy has a glue operand and simplify the checking logic. rdar://10930395 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05updated patch for the ARM fused multiply add/subSebastian Pop
In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper
static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Make aliases for shld and shrd match gas. PR12173.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen
MachineOperands that define part of a virtual register must have an <undef> flag if they are not intended as read-modify-write operands. The old trick of adding an <imp-def> operand doesn't work any longer. Fixes PR12177. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152008 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store register overlaps to reduce static data.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper
static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper
size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint8_t instead of enums to store values in X86 disassembler table. ↵Craig Topper
Shaves 150k off the size of X86DisassemblerDecoder.o git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-02Prevent obscure and incorrect tail-call optimization.Chad Rosier
In this instance we are generating the tail-call during legalizeDAG. The 2nd floor call can't be a tail call because it clobbers %xmm1, which is defined by the first floor call. The first floor call can't be a tail-call because it's not in the tail position. The only reasonable way I could think to fix this in a target-independent manner was to check for glue logic on the copy reg. rdar://10930395 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Neuter the optimization I implemented with r107852 and r108258 which turn someEvan Cheng
floating point equality comparisons into integer ones with -ffast-math. The issue is the optimization causes +0.0 != -0.0. Now the optimization is only done when one side is known to be 0.0. The other side's sign bit is masked off for the comparison. rdar://10964603 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister().Jakob Stoklund Olesen
This function could have r12 live across a function call when compiling thumb1 code. The test case for this is not included because it is very long. It must provoke emergency spilling near a function call. The behavior is provoked by MultiSource/Applications/JM/lencod, and it triggers an assertion in the scavenger. <rdar://problem/10963642> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01ARM use the right opcode for FP<->Integer move in fast-isel.Jim Grosbach
rdar://10965031 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Minimal changes for LLVM to compile under VS11.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Changes for migrating to using register mask operands.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151847 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Change ARMInstPrinter::printPredicateOperand() so it will not abort if itKevin Enderby
runs into the undefined 15 condition code value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Fix bugs which were introduced when support for base+index floating point loadsAkira Hatanaka
and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Make TargetRegisterClasses non-virtual by making the only virtual function a ↵Benjamin Kramer
function pointer. This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static initializer and a ton of cruft from the generated code. Shrinks ARMBaseRegisterInfo.o by ~100k. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Emit the "is an intrinsic overloaded" table as a bitfield.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Pass endian information to constructors. Define separate functions to createAkira Hatanaka
objects for big endian and little endian targets. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151788 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Added annotations for x86 pc relative loads to llvm's 'C' disassembler.Kevin Enderby
So with darwin's otool(1) an x86_64 hello world .o file will print: leaq L_.str(%rip), %rax ## literal pool for: Hello world git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Intel Atom instruction itineraries for mov sign extension and mov zero ↵Andrew Trick
extension. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29Make MemoryObject accessor members const againDerek Schuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28ARM implement TargetInstrInfo::getNoopForMachoTarget()Jim Grosbach
Without this hook, functions w/ a completely empty body (including no epilogue) will cause an MCEmitter assertion failure. For example, define internal fastcc void @empty_function() { unreachable } rdar://10947471 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28ARM vbit/vbif/vbsl assembly optional size suffix.Jim Grosbach
These instructions accept but do not require a size suffix. rdar://10947225 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng
direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Properly MCize the section switch, removing a FIXME.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151639 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar
prediction. ...", it is breaking the Clang build during the Compiler-RT part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28remove blanks, and some code formatJia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng
the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Add comments.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Do not reserve $gp as a dedicated global base register if the target ABI is ↵Akira Hatanaka
not O32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Add support for floating point base register + offset register addressing modeAkira Hatanaka
load and store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Enable ARM base pointer when calling functions with large arguments.Jakob Stoklund Olesen
When an outgoing call takes more than 2k of arguments on the stack, we don't allocate that call frame in the prolog, but adjust the stack pointer immediately before the call instead. This causes problems with the emergency spill slot because PEI can't track stack pointer adjustments on the second pass, and if the outgoing arguments are too big, SP can't be used to reach the emergency spill slot at all. Work around these problems by ensuring there is a base or frame pointer that can be used to access the emergency spill slot. <rdar://problem/10917166> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27This patch adds instruction latencies for the SSE instructionsPreston Gurd
to the instruction scheduler for the Intel Atom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151590 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Delete incorrect reference to inexistent Hexagon architecture manuals.Evandro Menezes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151582 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27ARM BL/BLX instruction fixups should use relocations.Jim Grosbach
We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Reapply r151278 with fixes.Roman Divacky
MCize function entry label emission on PowerPC64 properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Add q suffix aliases for the fistp and fisttp mnemonics.Chad Rosier
rdar://10921670 PR11935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Remove unnecessary template parameters.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Fix instruction predicates that were not set correctly.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Fix the symbolic operand added for the C disassmbler API for the ARM blKevin Enderby
thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151530 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27Remove HexagonGenIntrinsics.inc from Hexagon cmake file. It does not appear ↵Craig Topper
in the Makefile and the output it produces isn't used. The Hexagon intrinsics are all in the global Intrinsics.gen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151514 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27delete useless comment&blankJia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151512 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper
Kay Tiong Khoo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-26Default TargetData alignment information for 128-bit floating-point types.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151473 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-25Revert r151278, breaks static linking.Hal Finkel
Reverting this because it breaks static linking on ppc64. Specifically, it may be linkonce_odr functions that are the problem. With this patch, if you link statically, calls to some functions end up calling their descriptor addresses instead of calling to their entry points. This causes the execution to fail with SIGILL (b/c the descriptor address just has some pointers, not code). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151433 91177308-0d34-0410-b5e6-96231b3b80d8
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