aboutsummaryrefslogtreecommitdiff
path: root/lib/Target
AgeCommit message (Collapse)Author
2012-03-16ARM vmrs system registers mvfr0 and mvfr1 handling.Jim Grosbach
rdar://11058464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Remove inadvertant commit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152870 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15[fast-isel] Address Eli's comments for r152847. Specifically, add a test caseChad Rosier
and still allow immediate encoding, just not with cmn. rdar://11038907 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15[fast-isel] Don't try to encode LONG_MIN using cmn instructions.Chad Rosier
rdar://11038907 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152847 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15ARM case-insensitive checking for APSR_nzcv.Jim Grosbach
rdar://11056591 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.Jim Grosbach
rdar://11056647 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints onLang Hames
register allocation by allowing all 32 D-registers to be used. Patch by Cameron Zwarich. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Fix VCVT decoding (between floating-point and fixed-point, Floating-point). ↵Kristof Beyls
Patch by Richard Barton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15[avx] Add patterns for VINSERTF128rm.Chad Rosier
This results in things such as vmovaps -96(%rbx), %xmm1 vinsertf128 $1, %xmm1, %ymm0, %ymm0 to be combined to vinsertf128 $1, -96(%rbx), %ymm0, %ymm0 rdar://10643481 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Change the X86 assembler to not require a segment register on stringKevin Enderby
instruction's destination operand like it does for the source operand. Also fix a typo in the comment for X86AsmParser::isSrcOp(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-12Added a missing error check for X86 assembly with mismatched base and indexKevin Enderby
registers not both being 64-bit or both being 32-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-12Switch to unified syntax for VFP instructions in inline assembly.Bob Wilson
<rdar://problem/11024696> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Remove global map. This code isn't even hot.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Convert more static tables of registers used by calling convention to ↵Craig Topper
uint16_t to reduce space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper
specific backends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Remove unused functions getArgRegs and getNumArgRegs.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152535 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11llvm::SwitchInstStepan Dyatkovskiy
Renamed methods caseBegin, caseEnd and caseDefault with case_begin, case_end, and case_default. Added some notes relative to case iterators. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10*fix typo in comment; test of commit accessKay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152507 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10C files in llvm still have to be C89 compliant, remove C++-style comments.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152495 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.Bill Wendling
Patch by Kay Tiong Khoo! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10Do not custom lower i64 nodes if i64 is not a legal type. Move lines that setAkira Hatanaka
operation action of nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152452 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Lower SETCC nodes during legalization. Previously, it was lowered in DAG ↵Akira Hatanaka
combine pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152450 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Remove unused header files.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152447 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Add the missing call to Error when a bad X86 scale expression is parsed.Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152443 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Fix the x86 disassembler to at least print the lock prefix if it is the firstKevin Enderby
prefix. Added a FIXME to remind us this still does not work when it is not the first prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Use uint16_t to store opcodes in static tables in X86 backend.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152391 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Fix undefined behavior in the Mips backend.Ahmed Charles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152390 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09Fix a regression from r147481.Chad Rosier
Original commit message from r147481: DAGCombine for transforming 128->256 casts into a vmovaps, rather then a vxorps + vinsertf128 pair if the original vector came from a load. Fix: Unaligned loads need to generate a vmovups. rdar://10974078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*". ConstCaseIt is just a read-only iterator. CaseIt is read-write iterator; it allows to change case successor and case value. Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters. Main way of iterator usage looks like this: SwitchInst *SI = ... // intialize it somehow for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) { BasicBlock *BB = i.getCaseSuccessor(); ConstantInt *V = i.getCaseValue(); // Do something. } If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method. If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method. There are also related changes in llvm-clients: klee and clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08Invoke setTargetDAGCombine for SELECT.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152290 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08Swap the operands of a select node if the false (the second) operand is 0.Akira Hatanaka
For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152285 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08Set minimum function alignment to 3 if target is Mips64.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152282 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08This patch eliminates redundant instructions that produce 0.Akira Hatanaka
For example, the first instruction in the code below can be eliminated if the use of $vr0 is replaced with $zero: addiu $vr0, $zero, 0 add $vr2, $vr1, $vr0 add $vr2, $vr1, $zero git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152280 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08ARM don't use MCRelaxAll, as it's not safe on ARM.Jim Grosbach
The ARM code generator makes aggressive assumptions about the encodings being selected for branches which MCRelaxAll invalidates. rdar://11006355 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152268 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07[fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point Chad Rosier
condition flags to CPSR. This allows us to simplify SelectCmp. Patch by Zonr Chang <zonr.xchg@gmail.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07ARM pre-v6 assembly parsing for umull/smull.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07ARM pre-v6 alias for 'nop' to 'mov r0, r0'Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152185 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Tidy up. Remove dead code that slipped into previous commit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152184 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach
Register pair, all lanes subscripting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Tidy up. Kill some dead code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Allow the same types in DPair as in QPR.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152129 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Convert PowerPC to register mask operands.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen
When an instruction only writes sub-registers, it is still necessary to add an <imp-def> operand for the super-register. When reloading into a virtual register, rewriting will add the operand, but when loading directly into a virtual register, the <imp-def> operand is still necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames
The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05ARM vpush/vpop assembler mnemonics accept an optional size suffix.Jim Grosbach
rdar://10988114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach
Use the new composite physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-22 23:33:46 +0000