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2010-09-02Move x86 specific shuffle mask decoding to its own header, it's also going ↵Bruno Cardoso Lopes
to be used elsewhere. Also trim trailing whitespaces git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02handle case where a register class is specifiedJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Now that register allocation properly considers reserved regs, simplify theJim Grosbach
ARM register class allocation order functions to take advantage of that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Mask out reserved registers when constructing the set of allocatable regs.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112828 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Fill in a missing comment.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson
after regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Replace unpckl_undef and unpckh_undef matching with target specific opcodesBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Move condition out to prepare for more matchingBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Remove checking for isUNPCKL_v_undef_Mask, the specific node is already ↵Bruno Cardoso Lopes
emitted for it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02become more strict about when it's safe to use X86ISD::MOVLPSBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Clang's -ccc-host-triple was ignoring the arch specifier on my triple,Eric Christopher
I don't need to implement this quite yet - and not for ConstantInt anyhow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02This should be TargetMaterializeConstant instead.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02One definition of isThumb is plenty, thanks.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112793 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Remove trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Rework arm fast-isel load and store handling. Move offset computationEric Christopher
into the "address selection" routine and handle constant materialization for stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02trivial cleanupJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112779 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Simplify the tGPR register class now that the register allocators know notJim Grosbach
to try to allocate reserved registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,Bob Wilson
add, and subtract operations with zero-extended or sign-extended vectors. Update tests. Add auto-upgrade support for the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Revert r112689, avoid those kind of checks cause they mess up with mmxBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Using target specific nodes for shuffle nodes makes the maskBruno Cardoso Lopes
check more strict, breaking some cases not checked in the testsuite, but also exposes some foldings not done before, as this example: movaps (%rdi), %xmm0 movaps (%rax), %xmm1 movaps %xmm0, %xmm2 movss %xmm1, %xmm2 shufps $36, %xmm2, %xmm0 now is generated as: movaps (%rdi), %xmm0 movaps %xmm0, %xmm1 movlps (%rax), %xmm1 shufps $36, %xmm1, %xmm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Some basic store support.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112752 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Add some more load types in.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01zap dead code.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01temporarily revert r112664, it is causing a decoding conflict, and Chris Lattner
the testcases should be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Use movlps, movlpd, movss and movsd specific nodes instead of pattern ↵Bruno Cardoso Lopes
matching with movlp pattern fragment git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01minor change, simplify some logicBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-01Move some functions around so they can be used for some other to come functionBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31We have a chance for an optimization. Consider this code:Bill Wendling
int x(int t) { if (t & 256) return -26; return 0; } We generate this: tst.w r0, #256 mvn r0, #25 it eq moveq r0, #0 while gcc generates this: ands r0, r0, #256 it ne mvnne r0, #25 bx lr Scandalous really! During ISel time, we can look for this particular pattern. One where we have a "MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND instruction to 0. Something like this (greatly simplified): %r0 = ISD::AND ... ARMISD::CMPZ %r0, 0 @ sets [CPSR] %r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR] All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR] when it's zero. The zero value will all ready be in the %r0 register and we only need to change it if the AND wasn't zero. Easy! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31Use x86 specific MOVSLDUP node, add more patterns to match it and remove ↵Bruno Cardoso Lopes
useless load nodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31Use x86 specific MOVSHDUP node and add more patterns to match itBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112657 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31And ANDS pattern to match the t2ANDS pattern.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31Make %EFLAGS unallocatable.Jakob Stoklund Olesen
No CCR virtual registers should exist, and %EFLAGS is used in ways that can surprise RegAllocFast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern ↵Bruno Cardoso Lopes
fragments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some ↵Bruno Cardoso Lopes
useless nodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31SP relative offsets need to be adjusted by the local allocation size whenJim Grosbach
determining if they're likely to be in range of the SP when resolving frame references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112624 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31this assert should just be a condition, since this function is just asking ifJim Grosbach
the offset is legally encodable, not actually trying to do the encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31- Cleanup some whitespaces.Bill Wendling
- Convert {0,1} and friends into 0b01, which is identical and more consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the ↵Bruno Cardoso Lopes
handling of those nodes when seeking for scalars inside vector shuffles git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31Rewrite slightly so we can expand for floating point types easier.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112568 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30If we have an unhandled type then assert, we shouldn't get here forEric Christopher
things we can't handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112559 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Expand MOVi32imm in ARM mode after regalloc. This providesAnton Korobeynikov
scheduling opportunities (extra instruction can go in between MOVT / MOVW pair removing the stall). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112546 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, whichBill Wendling
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this out! :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Remember to clear the shadow kill flag at the same time as clearing the realJakob Stoklund Olesen
kill flag. This could cause duplicate kill flags when the same register was used twice in a continuous sequence of STRs. There is no small test case. <rdar://problem/8218046> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Remove NEON vmovn intrinsic, replacing it with vector truncate operations.Bob Wilson
Auto-upgrade the old intrinsic and update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Make ARM add rN, sp, #imm instructions rematerializable. That's how the ↵Jim Grosbach
address of locals is calculated, so this should help relieve register pressure a bit. Recalculating the local address is almost always going to be better than spilling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112503 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30When expanding NEON VST pseudo instructions, if the original super-registerBob Wilson
operand is killed, add it to the expanded instruction as an implicit kill operand instead of marking the individual subregs with kill flags. This should work better in general and also handles the case for VST3 where one of the subregs was not referenced in the expanded instruction and so was not marked killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is theBill Wendling
optional modified register (instead of reg0). Along with r112461 it will make sure that the optional define of CPSR is marked as "def" and will thus mark the instructions using these classes (t2ANDS*) as setting the 's' flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila
The IDX was treated as byte index, not element index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29Fix whitespaces. No functionality changes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvmBob Wilson
IR add/sub operations with one or both operands sign- or zero-extended. Auto-upgrade the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112416 91177308-0d34-0410-b5e6-96231b3b80d8
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