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2008-09-04Add a first attempt at implementing stores for X86 fast isel using target hooks.Owen Anderson
Dan or Evan, please review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55764 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04Load from GV stub should be locally CSE'd.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55763 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04Remove code that pad number of bytes to pop for X86_FastCall CC. The code ↵Evan Cheng
doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55756 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04Add intrinsics for log, log2, log10, exp, exp2.Dale Johannesen
No functional change (and no FE change to generate them). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03Create HandlePHINodesInSuccessorBlocksFast, a version ofDan Gohman
HandlePHINodesInSuccessorBlocks that works FastISel-style. This allows PHI nodes to be updated correctly while using FastISel. This also involves some code reorganization; ValueMap and MBBMap are now members of the FastISel class, so they needn't be passed around explicitly anymore. Also, SelectInstructions is changed to SelectInstruction, and only does one instruction at a time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03Add X86 target hook to implement load (even from GlobalAddress).Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55693 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03Fix capitalization in #include of FastISel.h. This unbreaks the build on ↵Ted Kremenek
case-sensitive filesystems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03Unbreak fast isel.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55685 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-03Let tblgen only generate fastisel routines, not the class definition. This ↵Evan Cheng
makes it easier for targets to define its own fastisel class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55679 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02Fix some bugs in the code sequences for atomics.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55643 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02Add Mac OS X compatible JIT callback routine.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55625 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02Revamp ARM JIT.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55624 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02Change getBinaryCodeForInstr prototype. First operand MachineInstr& should ↵Evan Cheng
be const. Make corresponding changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55623 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01Control flow instruction encodings.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01ldm / stm instruction encodings.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01AXI2 and AXI3 instruction encodings.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01Reorganize instruction formats again; AXI1 encoding.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55597 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01addrmode3 instruction encodings.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01Reorganize some instruction format definitions. No functionality change.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55594 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-01Rest of addrmode2 instruction encodings.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31Addr2 word / byte load encodings.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31fix a bunch of 80-col violationsGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55588 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTRBill Wendling
instructions in CellSPU as "Expand" so that they won't be generated. I added a "FIXME" so that this hack can be addressed and reverted once ISD::ROTR is supported in the .td files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55582 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31Expand for ROTR with MVT::i64.Bill Wendling
Dale, Could you please review this? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55581 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30fix some 80-col violationsGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55565 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But ↵Evan Cheng
various passes cannot handle remating these. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55562 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 ↵Evan Cheng
shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30Add ppc partial-word ATOMIC_CMP_SWAP.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55554 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29Swap fp comparison operands and change predicate to allow load folding ↵Evan Cheng
(safely this time). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55553 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29Use static_cast instead of C style cast.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55552 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29Backing out 55521. Not safe.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29Add partial word version of ATOMIC_SWAP.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55546 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29Add initial support for fast isel of instructions that have inputs pinned to ↵Owen Anderson
physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29TableGen'ing instruction encodings.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 ↵Evan Cheng
encode the opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29MVN is addrmode1.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55530 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29More refactoring.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28Swap fp comparison operands and change predicate to allow load folding.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28Refactor ARM instruction format definitions into a separate file. No ↵Evan Cheng
functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28Add a target callback for FastISel.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28remove tabs, fix > 80 colsGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55511 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif
Node to reflect semantics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28In lowering SELECT_CC, removed cases where we can't flip the true and false ↵Mon P Wang
when the compare value has a NaN git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55499 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28Use resize instead of reserve. Reserve doesn't change size().Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55486 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28Implement partial-word binary atomics on ppc.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55478 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55466 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28Split the ATOMIC NodeType's to include the size, e.g.Dale Johannesen
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD. Increased the Hardcoded Constant OpActionsCapacity to match. Large but boring; no functional change. This is to support partial-word atomics on ppc; i8 is not a valid type there, so by the time we get to lowering, the ATOMIC_LOAD nodes looks the same whether the type was i8 or i32. The information can be added to the AtomicSDNode, but that is the largest SDNode; I don't fully understand the SDNode allocation, but it is sensitive to the largest node size, so increasing that must be bad. This is the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use theBill Wendling
SSE2 registers as well as the MMX registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55436 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-27Reinstate the x86-64 portion of r55190. When doing extloads intoDan Gohman
64-bit registers from 16-bit and smaller memory locations, prefer instructions that define the entire 64-bit register, to avoid partial-register updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55422 91177308-0d34-0410-b5e6-96231b3b80d8
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