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2003-05-31Renamed a variable.Vikram S. Adve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6472 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Minor changes.Vikram S. Adve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6470 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Added MachineCodeForInstruction object as an argument toVikram S. Adve
TmpInstruction constructors because every TmpInstruction object has to be registered with a MachineCodeForInstruction to prevent leaks. This simplifies the user's code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6469 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Changes to allow explicit physical register arguments that have beenVikram S. Adve
preallocated. While reg-to-reg dependences were already handled, this change required new code for adding edges to/from call instructions. This was part of the extensive changes to the way code generation occurs for function call arguments and return values. See log for CodeGen/PhyRegAlloc.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6467 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Several bug fixes: globals in call operands were not being pulled out;Vikram S. Adve
globals in some other places may not have been pulled out either; globals in phi operands were being put just before the phi instead of in the predecessor basic blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6466 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Extensive changes to the way code generation occurs for functionVikram S. Adve
call arguments and return values: Now all copy operations before and after a call are generated during selection instead of during register allocation. The values are copied to virtual registers (or to the stack), but in the former case these operands are marked with the correct physical registers according to the calling convention. Although this complicates scheduling and does not work well with live range analysis, it simplifies the machine-dependent part of register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6465 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Reverting previous beautification changes.Vikram S. Adve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6464 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Removed useless code -- the byte order of output code is correct as is.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6462 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31The 'rd' register is consistently mentioned last in instruction definitions.Misha Brukman
Created new classes from which instructions inherit their ordering of fields. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6461 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31* Put back into action SLL/SRL/SRA{r,i}6 instructionsMisha Brukman
* Fixed page numbers referring to the Sparc manual git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6460 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Code beautification, no functional changes.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6459 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Enabling some of these passes causes lli to breakMisha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6457 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31The actual order of parameters in a 2-reg-immediate assembly instructions isMisha Brukman
"rs1, imm, rd": most importantly, rd goes last. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6456 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30When converting virtual registers to immediate constants, change the opcode.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6452 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Added:Misha Brukman
* ability to save BasicBlock references to be resolved later * register remappings from the enum values to the real hardware numbers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6449 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Fixed the namespace to match SparcInternals.h; added notes on some missingMisha Brukman
sections of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6448 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30The register types need to be visible outside of the class to be useful.Misha Brukman
For one, converting register numbers based on class in the code emitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6447 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.Misha Brukman
Code beautification for the rest of the code: changed layout to match the rest of the code base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6446 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Make LLI behave just like LLC with regard to the compile passes it uses.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6444 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Made the register and immediate versions of instructions consecutive.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6439 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Because the format of the shift instructions is `shift r, shcnt, r', theMisha Brukman
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that implies that the two registers are the first two parameters to the instruction. Thus I made the instructions inherit from F3rd again, and manually added an rs1 field AFTER the shcnt field in the instruction, which maps to the appropriate place in the instruction. The other changes are just elimination of unnecessary spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6437 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.Brian Gaeke
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also, their fields were totally screwed up. This seems to fix the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6429 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 so far everything compilesGuochun Shi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6423 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29Since there is now another derived .inc file, ignore them all.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6411 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29Use an absolute path to TableGen because not everyone (e.g. automatic tester)Misha Brukman
has their path set up by this point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6410 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29Added the target-independent part of TableGen data.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6403 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29Eliminate unnecessary ->get calls that are now automatically handled.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6397 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29When TableGen finds an error in the SparcV9.td file, it exits with a non-zeroMisha Brukman
exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only much later, produces a link error because the key function that TableGen creates isn't found. Using a temporary file in the middle forces a good .INC file to be generated by TableGen, and it will keep trying until you fix the input file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6392 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29Fixed to use the correct format of the instruction.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6390 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29This should work better with re-generating the SparcV9CodeEmitter.inc file.Misha Brukman
Also, added a rule to delete the generated .inc file on `make clean'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6389 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29* Broke up SparcV9.td into separate files as it was getting unmanageableMisha Brukman
* Added some Format 4 classes, but not instructions * Added notes on missing sections with FIXMEs * Added RDCCR instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28Fixed ordering of elements in instructions: although the binary instructionsMisha Brukman
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is instr rd, imm, rs1, and that is how they are constructed in the instruction selector. This fixes the discrepancy. Also fixed some comments along the same lines and fixed page numbers referring to where instructions are described in the Sparc manual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6384 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28Add dependency to make TableGen rule fire.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6383 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Fixed an error preventing compilation.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6381 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added the 'r' and 'i' annotations to instructions as their opcode names haveMisha Brukman
changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6380 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Keep track of the current BasicBlock being processed so that a referencingMisha Brukman
MachineInstr can later be patched up correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6378 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added 'r' and 'i' annotations to instructions as SparcInstr.def has changed.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6377 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman
Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman
Here I had to make one non-trivial change: add a function to get a version of the opcode that takes an immediate, given an opcode that takes all registers. This is required because sometimes it is not known at construction time which opcode is used because opcodes are passed around between functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6375 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6373 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added entries for each of the instructions with annotations ('r' or 'i').Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6372 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27One of the first major changes to make the work of JITting easier: addingMisha Brukman
annotations on instructions to specify which format they are (i.e., do they take 2 registers and 1 immediate or just 3 registers) as that changes their binary representation and hence, code emission. This makes instructions more like how X86 defines them to be. Now, writers of instruction selection must choose the correct opcode based on what instruction type they are building, which they already know. Thus, the JIT doesn't have to do the same work by `discovering' which operands an instruction really has. As this involves lots of small changes to a lot of files in lib/target/Sparc, I'll commit them individually because otherwise the diffs will be unreadable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6371 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27* Allow passing in an unsigned configuration to allocateSparcTargetMachine()Misha Brukman
a default value is set in the header file. * Fixed some code layout to make it more consistent with the rest of codebase * Added addPassesToJITCompile() with relevant passes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6369 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Moved generation of the SparcV9CodeEmitter.inc file higher in the Makefile soMisha Brukman
that Makefile.common would see it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6367 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Add prototypes to add passes to JIT compilation and code emission.Misha Brukman
Also, added annotations to how instructions are modified (reg/imm operands). Added prototype for adding register numbers to values pass for interfacing with the target-independent register allocators in the JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6366 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Broke out class definition from SparcV9CodeEmitter, and added ability to take aMisha Brukman
MachineCodeEmitter to make a pass-through debugger -- output to memory and to std::cerr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6363 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27SparcV9CodeEmitter.cpp is a part of the Sparc code emitter. The main functionMisha Brukman
that assembles instructions is generated via TableGen (and hence must be built before building this directory, but that's already the case in the top-level Makefile). Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc', which is included by SparcV9CodeEmitter.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6357 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added definitions for a bunch of floating-point instructions.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6356 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()Vikram S. Adve
and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6342 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27(1) Added special register class containing (for now) %fsr.Vikram S. Adve
Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. (3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly() and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
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