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2013-05-13Remove the MachineMove class.Rafael Espindola
It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-11Change getFrameMoves to return a const reference.Rafael Espindola
To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-10Remove unused argument.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-09[XCore] Fix handling of functions where only the LR is spilled.Richard Osborne
Previously we only checked if the LR required saving if the frame size was non zero. However because the caller reserves 1 word for the callee to use that doesn't count towards our frame size it is possible for the LR to need saving and for the frame size to be 0. We didn't hit when the LR needed saving because of a function calls because the 1 word of stack we must allocate for our callee means the frame size is always non zero in this case. However we can hit this case if the LR is clobbered in inline asm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05[XCore] Add LDAPB instructions.Richard Osborne
With the change the disassembler now supports the XCore ISA in its entirety. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05[XCore] Update LDAP to use pcrel_imm.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181154 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05[XCore] Rename calltarget -> pcrel_imm.Richard Osborne
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181153 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05[XCore] Add BLRB instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05[XCore] Remove '-' from back branch asm syntax.Richard Osborne
Instead operands are treated as negative immediates where the sign bit is implicit in the instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04Fix buildbot failure on 64 bit linux due to std::max() having differentRichard Osborne
operand types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181128 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04[XCore] Remove unused operand type.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181127 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04[XCore] Make use of the target independent global address offset folding.Richard Osborne
This let us to remove some custom code that matched constant offsets from globals at instruction selection time as a special addressing mode. No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04[XCore] Simplify code that checks for an aligned base plus a constant.Richard Osborne
The code now makes use of ComputeMaskedBits, SelectionDAG::isBaseWithConstantOffset and TargetLowering::isGAPlusOffset where appropriate reducing the amount of logic needed in XCoreISelLowering. No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04[XCore] Move lowering of thread local storage to a separate pass.Richard Osborne
Thread local storage is not supported by the XMOS linker so we handle thread local variables by lowering the variable to an array of n elements (where n is the number of hardware threads per core, currently 8 for all XMOS devices) indexed by the the current thread ID. Previously this lowering was spread across the XCoreISelLowering and the XCoreAsmPrinter classes. Moving this to a separate pass should be much cleaner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04[XCore] Use static relocation model by default.Richard Osborne
This allows us to get get rid of a hack in XCoreTargetObjectFile where the the DataRel* sections were overridden. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ArrayRefize getMachineNode(). No functionality change.Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04[XCore] Add bru instruction.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04[XCore] The RRegs register class is a superset of GRRegs.Richard Osborne
At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22Allow the register scavenger to spill multiple registersHal Finkel
This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard
LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Fix PR10475Michael Liao
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky
to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Update TargetLowering ivars for name policy.Jim Grosbach
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly ivars should be camel-case and start with an upper-case letter. A few in TargetLowering were starting with a lower-case letter. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17[XCore] Add missing 2r instructions.Richard Osborne
These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17[XCore] Add TSETR instruction.Richard Osborne
This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17[XCore] Add missing u10 / lu10 instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17[XCore] Add missing u6 / lu6 instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to XCore return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174414 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31[PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier
Each target implementation was needlessly recomputing the index. Part of rdar://13076458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2rus instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 1r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 0r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l4r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Use the correct format in the STW / SETPSC instruction names.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Fix order of operands for crc8_l4rRichard Osborne
The order in which operands appear in the encoded instruction is different to order in which they appear in assembly. This changes the XCore backend to use the instruction encoding order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l5r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Fix order of operands for l5r instructions.Richard Osborne
With this change the operands order matches the order in which the operands are encoded in the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Use correct mnemonic / instruction name for ldivu.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Add instruction encodings / disassembly support for l6r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Fix some incorrectly named u10 / lu10 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Remove unused multiclass.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Add instruction encodings / disassembly support for u6 / lu6 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Add instruction encoding / disassembly support for ru6 / lru6 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Use correct format for the LDAWCP instruction (u6).Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support for l2rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support for l3r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembler support for 2rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support 3r instructions.Richard Osborne
It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
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