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2012-08-18Refactor code a bit to reduce number of calls in the final compiled code. No ↵Craig Topper
functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18Revert r162160 because it made a few buildbots fail.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18The X86 backend has a number of optimizations for SETCC nodes which useNadav Rotem
arithmetic instructions. However, when small data types are used, a truncate node appears between the SETCC node and the arithmetic operation. This patch adds support for this pattern. Before: xorl %esi, %edi testb %dil, %dil setne %al ret After: xorb %dil, %sil setne %al ret rdar://12081007 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162160 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Use nested switch to select arguments to reduce calls to EmitPCMP.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to ↵Craig Topper
reduce to only a single call to it thus allowing it to be inlined by the compiler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.Anitha Boyapati
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162012 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162010 ↵Anitha Boyapati
91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14minor fix of X86ISD::VSEXT_MOVL dumpMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14fix PR11334Michael Liao
- FP_EXTEND only support extending from vectors with matching elements. This results in the scalarization of extending to v2f64 from v2f32, which will be legalized to v4f32 not matching with v2f64. - add X86-specific VFPEXT supproting extending from v4f32 to v2f64. - add BUILD_VECTOR lowering helper to recover back the original extending from v4f32 to v2f64. - test case is enhanced to include different vector width. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161894 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14Factor duplicate calls to getUNDEF in several functions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161860 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14Re-factor intrinsic lowering to combine common parts of similar intrinsics. ↵Craig Topper
Reduces compiled code size a little bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr fromManman Ren
OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13X86: when auto-detecting the subtarget features, make sure use IsIntel to detectManman Ren
Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161763 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and ↵Craig Topper
putting an a couple if conditions in a better order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161746 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Refactor code a bit to share commonalities. No functional change intended.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Fix an unused variable warning from r161742.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13Remove the LowerMMXCONCAT_VECTORS function. It could never execute because ↵Craig Topper
there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Remove call to setOperationAction for SETCC of v4f32. SETCC returns an ↵Craig Topper
integer type not an FP type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Remove unnecessary call to setOperationAction for SETCC of v2i64 under ↵Craig Topper
SSE42. It was already called for the same under SSE2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Make replace many calls to getSizeInBits() with is128BitVector/is256BitVectorCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Use MVT.isXBitVector instead of EVT.isXBitVector when setting up operation ↵Craig Topper
actions. Compiles to smaller code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11fix PR13577, an issue introduced by r161687Michael Liao
- FCMOV only supports a subset of X86 conditions. Skip boolean simplification if X86 condition is not valid for FCMOV. - add a minimal test case for PR13577. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161732 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11Move setOperationAction for CONCAT_VECTORS for 256-bit vectors into loop ↵Craig Topper
since all 256-bit types are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11Tidy up indentation. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11Fix a cast that was casting away 'const' unnecessarily Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11Add a couple default: llvm_unreachable() to some switch statements. Fix a ↵Craig Topper
bad message in an existing llvm_unreachable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10X86: when we are auto-detecting the subtarget features, make sure we turn onManman Ren
FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge. FeatureFastUAMem is already on if we pass in nehalem or westmere as a command argument. rdar: 7252306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10add X86-specific DAG optimization to simplify boolean testMichael Liao
- if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value generated from X86ISD::SETCC, try to simplify the boolean value generation and checking by reusing the original EFLAGS with proper condition code - add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places consuming EFLAGS part of patches fixing PR12312 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10remove tailing whitespaces and test commitMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10Add some missing includes for the build against stdcxx.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09[ms-inline asm] Extend the MC AsmParser API to match MCInsts (but not emit).Chad Rosier
This new API will be used by clang to parse ms-style inline asms. One goal of this project is to use this style of inline asm for targets other then x86. Therefore, this API needs to be implemented for non-x86 targets at some point in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161624 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08X86: enable CSE between CMP and SUBManman Ren
We perform the following: 1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering. 2> Modify MachineCSE to correctly handle implicit defs. 3> Convert SUB back to CMP if possible at peephole. Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled by peephole now. rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08Don't scan physreg use-def chains looking for a PIC base.Jakob Stoklund Olesen
We can't rematerialize a PIC base after register allocation anyway, and scanning physreg use-def chains is very expensive in a function with many calls. <rdar://problem/12047515> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07X86 cmp lowering is looking past truncate on the condition node. It should onlyEvan Cheng
do so when the high bits are known zero. This caused a subtle miscompilation. rdar://12027825 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.Andrew Trick
This allows codegen passes to query properties like InstrItins->SchedModel->IssueWidth. It also ensure's that computeOperandLatency returns the X86 defaults for loads and "high latency ops". This should have no significant impact on existing schedulers because X86 defaults happen to be the same as global defaults. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06Add support for the OpenBSD for Bitrig.Eric Christopher
Patch by David Hill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires ↵Craig Topper
custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-05Remove custom inserter for MWAIT. It doesn't do anything that couldn't be ↵Craig Topper
represented in a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161306 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-05Use a COPY node instead of an explicit MOVA opcode in the custom insterter ↵Craig Topper
for pcmpestrm/pcmpistrm. Allows the register allocator to handle it better and prevent wasted identity moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Fall back to selection DAG isel for calls to builtin functions.Bob Wilson
Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Add more comments and use early returns to reduce nesting in isLoadFoldable. Also disable folding for V_SET0 to avoid introducing a const pool entry and a const pool load. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01X86: mark GATHER instructios as mayLoadManman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Added FMA functionality to X86 target.Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper
used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31[x86 frame lowering] In 32-bit mode, use ESI as the base pointer.Chad Rosier
Previously, we were using EBX, but PIC requires the GOT to be in EBX before function calls via PLT GOT pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Make INSTRUCTION_SPECIFIER_FIELDS match X86DisassemblerCommon.h. Also remove ↵Craig Topper
trailing whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Tidy up trailing whitespaceCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Tidy up trailing whitespaceCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161026 91177308-0d34-0410-b5e6-96231b3b80d8
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