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2012-09-13Don't fold indexed loads into TCRETURNmi64.Jakob Stoklund Olesen
We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Fix PR11985Michael Liao
- BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12[ms-inline asm] Make the operand size directives case insensitive.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Add support for AMD Geode.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163710 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Indentation fixes. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163682 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Release build: guard dump functions withManman Ren
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11StringSwitchify.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Simplify logic. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163648 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Make a bunch of lowering helper functions static instead of member ↵Craig Topper
functions. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163596 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Change unsigned to a uint16_t in static disassembler tables to reduce the ↵Craig Topper
table size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163594 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Update function names to conform to guidelines. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Revert r163556. Missed updates to tablegen files.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Update function names to conform to guidelines. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Remove redundant semicolons which are null statements.Dmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10[ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() functionChad Rosier
and update the printOperand() function accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10[ms-inline asm] Add support for .att_syntax directive.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Enhance PR11334 fix to support extload from v2f32/v4f32Michael Liao
- Fix an remaining issue of PR11674 as well git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10Add boolean simplification support from CMOVMichael Liao
- If a boolean value is generated from CMOV and tested as boolean value, simplify the use of test result by referencing the original condition. RDRAND intrinisc is one of such cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163516 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10The VPSHUFB 256-bit instruction may be generated when one of input vector is ↵Elena Demikhovsky
undefined or zeroinitializer. I've added the "zeroinitializer" case in this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163506 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-09Add missing space before {. No functionality change.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163484 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163473 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08Use 256-bit alignment for constant pool value for 256-bit vector FNEG lowering.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163463 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08Add support for lowering FABS of vector types.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper
FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163458 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer
registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163390 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Release build: guard dump functions with "ifndef NDEBUG"Manman Ren
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06AVX2 optimization.Elena Demikhovsky
Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Remove duplicated helper functionMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163295 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Use iPTR instead of i32 for extract_subvector/insert_subvector index in ↵Craig Topper
lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Add patterns for converting stores of subvector_extracts of lower 128-bits ↵Craig Topper
of a 256-bit vector to VMOVAPSmr/VMOVUPSmr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Stop casting away const qualifier needlessly.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Use const properly so that we dont remove const qualifier from region and MIIRoman Divacky
by casting. Found with gcc48. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163247 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Remove some of the patterns added in r163196. Increasing the complexity on ↵Craig Topper
insert_subvector into undef accomplishes the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163198 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Add patterns for integer forms of VINSERTF128/VINSERTI128 folded with loads. ↵Craig Topper
Also add patterns to turn subvector inserts with loads to index 0 of an undef into VMOVAPS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG ↵Craig Topper
build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163192 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Fix function name per coding standard.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163187 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04Generic Bypass Slow DivPreston Gurd
- CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04This patch optimizes shuffle instruction - generates 2 instructions instead ↵Elena Demikhovsky
of 4. Since this specific shuffle is widely used in many workloads we have ~10% performance on them. shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> vmovaps (%rdx), %ymm0 vshufps $8, %ymm0, %ymm0, %ymm0 vmovaps (%rcx), %ymm1 vshufps $8, %ymm0, %ymm1, %ymm1 vunpcklps %ymm0, %ymm1, %ymm0 vmovaps (%rcx), %ymm0 vmovsldup (%rdx), %ymm1 vblendps $85, %ymm0, %ymm1, %ymm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, addChad Rosier
the NumMCOperands argument to the GetMCInstOperandNum() function that is set to the number of MCOperands this asm operand mapped to. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Add an interface to the GetMCInstOperandNum() function in theChad Rosier
MCTargetAsmParser class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03Removed unused argument.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03some peepholes that should match horizontal add/sub operations.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03[ms-inline asm] Expose the Kind and Opcode variables from theChad Rosier
MatchInstructionImpl() function. These values are used by the ConvertToMCInst() function to index into the ConversionTable. The values are also needed to call the GetMCInstOperandNum() function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-01TyposCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31SelectionDAG: when constructing VZEXT_LOAD from other loads, make sure itsManman Ren
output chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://11457792 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Mark FMA4 instructions as commutable and add them to the folding tables.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163035 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Add selection of RegOp2MemOpTable3 to canFoldMemoryOperandCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Fix PR12359Michael Liao
- In addition to undefined, if V2 is zero vector, skip 2nd PSHUFB and POR as well as PSHUFB will zero elements with negative indices. Patch by Sriram Murali <sriram.murali@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163018 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31The ConvertToMCInst() function can't fail, so remove the now dead ↵Chad Rosier
Match_ConversionFail enum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31Mark FMA3 instructions as commutable so that the operands to the multiply ↵Craig Topper
part can be commuted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163001 91177308-0d34-0410-b5e6-96231b3b80d8
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