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2012-10-17Check SSSE3 instead of SSE4.1Michael Liao
- All shuffle insns required, especially PSHUB, are added in SSSE3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17Fix setjmp on models with non-Small code model nor non-Static relocation modelMichael Liao
- MBB address is only valid as an immediate value in Small & Static code/relocation models. On other models, LEA is needed to load IP address of the restore MBB. - A minor fix of MBB in MC lowering is added as well to enable target relocation flag being propagated into MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166084 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Support v8f32 to v8i8/vi816 conversion through custom loweringMichael Liao
- Add custom FP_TO_SINT on v8i16 (and v8i8 which is legalized as v8i16 due to vector element-wise widening) to reduce DAG combiner and its overhead added in X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Reapply r165661, Patch by Shuxin Yang <shuxin.llvm@gmail.com>.NAKAMURA Takumi
Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". Original message since r165661: My previous change has a bug: I negated the condition code of a CMOV, and go ahead creating a new CMOV using the *ORIGINAL* condition code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166017 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Move X86MCInstLower class definition into implementation file. It's not ↵Craig Topper
needed outside. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Add __builtin_setjmp/_longjmp supprt in X86 backendMichael Liao
- Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also used as a light-weight replacement of setjmp/longjmp which are used to implementation continuation, user-level threading, and etc. The support added in this patch ONLY addresses this usage and is NOT intended to support SjLj exception handling as zero-cost DWARF exception handling is used by default in X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165989 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15[ms-inline asm] If we parsed a statement and the opcode is valid, then it's ↵Chad Rosier
an instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15[ms-inline asm] Update the end loc for ParseIntelMemOperand.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Resubmit the changes to llvm core to update the functions to support ↵Micah Villmow
different pointer sizes on a per address space basis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-13X86: Disable long nops for all cpus prior to pentiumpro/i686.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-13X86: Fix accidentally swapped operands.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165871 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-13X86: Promote i8 cmov when both operands are coming from truncates of the ↵Benjamin Kramer
same width. X86 doesn't have i8 cmovs so isel would emit a branch. Emitting branches at this level is often not a good idea because it's too late for many optimizations to kick in. This solution doesn't add any extensions (truncs are free) and tries to avoid introducing partial register stalls by filtering direct copyfromregs. I'm seeing a ~10% speedup on reading a random .png file with libpng15 via graphicsmagick on x86_64/westmere, but YMMV depending on the microarchitecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165868 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-13[ms-inline asm] Remove the MatchInstruction() function. Previously, this wasChad Rosier
the interface between the front-end and the MC layer when parsing inline assembly. Unfortunately, this is too deep into the parsing stack. Specifically, we're unable to handle target-independent assembly (i.e., assembly directives, labels, etc.). Note the MatchAndEmitInstruction() isn't the correct abstraction either. I'll be exposing target-independent hooks shortly, so this is really just a cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165858 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12[ms-inline asm] Capitalize per coding standard.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165847 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12[ms-inline asm] Use the new API introduced in r165830 in lieu of theChad Rosier
MapAndConstraints vector. Also remove the unused Kind argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Revert 165732 for further review.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Add in the first iteration of support for llvm/clang/lldb to allow variable ↵Micah Villmow
per address space pointer sizes to be optimized correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Revert r165661, "Patch by Shuxin Yang <shuxin.llvm@gmail.com>."NAKAMURA Takumi
It broke stage2 clang and test-suite/MultiSource/Benchmarks/mediabench/g721/g721encode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Change MachineInstrBuilder::addDisp to copy over target flags by default.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165677 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem
information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Patch by Shuxin Yang <shuxin.llvm@gmail.com>.Nadav Rotem
Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add support for FP_ROUND from v2f64 to v2f32Michael Liao
- Due to the current matching vector elements constraints in ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from v2f32) is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPROUND to work around this constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add alternative support for FP_ROUND from v2f32 to v2f64Michael Liao
- Due to the current matching vector elements constraints in ISD::FP_EXTEND, rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPEXT to work around this constraints. This patch also reverts a previous attempt to fix this issue by recovering the scalarized ISD::FP_EXTEND pattern and thus significantly reduces the overhead of supporting non-power-2 vector FP extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09When expanding atomic load arith instructions, do not lose target flags. ↵Evan Cheng
rdar://12453106 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Use the attribute enums to query if a parameter has an attribute.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Create enums for the different attributes.Bill Wendling
We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165488 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Separate AVXCC and SSECC printing for cmpps/pd/ss/sd and add masking before ↵Craig Topper
the switch statement. This keeps the unreachable default case from being hit if the instruction was created with an intrinsic with too large of an immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165483 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Remove some unused code in the X86AsmPrinter. Add LLVM_OVERRIDE and virtual ↵Craig Topper
keywords to the remaining interface methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165478 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08misched: remove the unused getSpecialAddressLatency hook.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165418 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Move TargetData to DataLayout.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-07X86: fcmov doesn't handle all possible EFLAGS, fall back to a branch for the ↵Benjamin Kramer
others. Otherwise it will try to use SSE patterns and fail horribly if sse is disabled. Fixes PR14035. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165377 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05[ms-inline asm] Add a few typedefs to simplify future changes.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165324 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05Remove some encoding bits I forgot to remove from SETB_C16r and SETB_C64r in ↵Craig Topper
r165302. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05Move expansion of SETB_C(8/16/32/64)r from MCInstLower to ↵Craig Topper
ExpandPostRAPseudos and mark them as pseudos in the td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05Follow up to r165072. Try a different approach: only move the load when it's ↵Evan Cheng
going to be folded into the call. rdar://12437604 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165287 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04[ms-inline asm] Add support for parsing [Intel dialect] memory operands that useChad Rosier
segmented registers. Test case to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165275 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04This patch corrects commit 165126 by using an integer bit width instead of Preston Gurd
a pointer to a type, in order to remove the uses of getGlobalContext(). Patch by Tyler Nowicki. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Update this a bit more to represent how the prologue should work:Eric Christopher
a) frame setup instructions define the prologue b) we shouldn't change our location mid-stream Add a test to make sure that the stack adjustment stays within the prologue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Add register encoding support in X86 backendMichael Liao
- Add 'HwEncoding' for X86 registers and call getEncodingValue() to retrieve their encoding values. - This's the first step to adopt new scheme. Furthur revising is onging. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165241 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Use new accessor methods to query for attributes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Clean up tailing whitespacesMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165182 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03[ms-inline asm] Add support in the X86AsmPrinter for printing memory referencesChad Rosier
in the Intel syntax. The MC layer supports emitting in the Intel syntax, but this would require the inline assembly MachineInstr to be lowered to an MCInst before emission. This is potential future work, but for now emitting directly from the MachineInstr suffices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Typos.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165141 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Add methods which query for the specific attribute instead of using theBill Wendling
enums. This allows for better encapsulation of the Attributes class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Set up MCSchedModel after detecting the CPU type in X86SubTarget.Preston Gurd
Corrects a problem whereby MCSchedModel was not being set up when the CPU type was auto-detected. Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Revert 165051-165049 while looking into the foreach.m failure inEric Christopher
more detail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Fix 80-column violationCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen
Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Fix a serious X86 instruction selection bug. InEvan Cheng
X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside callseq_start / callseq_end so it can be folded into a call. This can create a cycle in the DAG when the call is glued to a copytoreg. We have been lucky this hasn't caused too many issues because the pre-ra scheduler has special handling of call sequences. However, it has caused a crash in a specific tailcall case. rdar://12393897 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Revert "Don't use a debug location for frame setup instructions in the"Eric Christopher
This reverts 165055 and 165052 temporarily while I look at debugger failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165071 91177308-0d34-0410-b5e6-96231b3b80d8
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