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2013-01-28Fix 256-bit PALIGNR comment decoding to understand that it works on ↵Craig Topper
independent 256-bit lanes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173674 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Add missing break in 256-bit palignr comment printing. No test case yet ↵Craig Topper
because the comment itself is still wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173669 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-28Fix inconsistent usage of PALIGN and PALIGNR when referring to the same ↵Craig Topper
instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-26X86: Do splat promotion later, so the optimizer can chew on it first.Benjamin Kramer
This catches many cases where we can emit a more efficient shuffle for a specific mask or when the mask contains undefs. Once the splat is lowered to unpacks we can't do that anymore. There is a possibility of moving the promotion after pshufb matching, but I'm not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so I avoided that for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky
(defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24Moving Cost Tables up to share with other targetsRenato Golin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Fix an issue of pseudo atomic instruction DAG scheduleMichael Liao
- Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer
rip-rel relocations will be off by one byte. PR15040. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Initial patch for x32 ABI support.Eli Bendersky
Add the x32 environment kind to the triple, and separate the concept of pointer size and callee save stack slot size, since they're not equal on x32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Make APFloat constructor require explicit semantics.Tim Northover
Previously we tried to infer it from the bit width size, with an added IsIEEE argument for the PPC/IEEE 128-bit case, which had a default value. This default value allowed bugs to creep in, where it was inappropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Use <0 checks in place of ==-1 because it results in simpler code.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Use MVT instead of EVT in LowerVECTOR_SHUFFLEtoBlend.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Remove trailing whitespace.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Fix some 80 column violations.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Make helper method static.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Convert more EVT's to MVT's in the lowering methods.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172995 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Capitalize lowerTRUNCATE so that it matches the other lower functions in ↵Craig Topper
this file despite it not matching coding standards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172994 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Revert CostTable algorithm, will re-writeRenato Golin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Make LowerVSETCC a static function and use MVT instead of EVT.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172969 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Revert 172708.Nadav Rotem
The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends. This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical. Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Make some helper methods static.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172936 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Remove DebugLoc argument from static function. It can easily be obtained ↵Craig Topper
from the SVOp passed in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172935 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Use MVT instead of EVT in more instruction lowering code.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172933 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19Use MVT instead of EVT in more of the shuffle lowering code.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172930 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19Capitalize LowerVectorIntExtend to be consistent with all the other lower ↵Craig Topper
functions in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19On Sandybridge split unaligned 256bit stores into two xmm-sized stores. Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172894 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19Use MVT instead of EVT when computing shuffle immediates since they can only ↵Craig Topper
be for legal types. Keeps compiler from generating unneeded checks and handling for extended types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172893 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18On Sandybridge loading unaligned 256bits using two XMM loads (vmovups and ↵Nadav Rotem
vinsertf128) is faster than using a single vmovups instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172868 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18Calculate vector element size more directly for VINSERTF128/VEXTRACTF128 ↵Craig Topper
immediate handling. Also use MVT since this only called on legal types during pattern matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18Minor formatting fix. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172795 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18Spelling fix: extened->extended. Trailing whitespace in same function.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172793 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18Make more use of is128BitVector/is256BitVector in place of getSizeInBits() ↵Craig Topper
== 128/256. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18[ms-inline asm] Make the error message more generic now that we support the Chad Rosier
'SIZE' and 'LENGTH' operators. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17[ms-inline asm] Add support for the 'SIZE' and 'LENGTH' operators.Chad Rosier
Part of rdar://12576868 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172743 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Optimization for the following SIGN_EXTEND pairs:Elena Demikhovsky
v8i8 -> v8i64, v8i8 -> v8i32, v4i8 -> v4i64, v4i16 -> v4i64 for AVX and AVX2. Bug 14865. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172708 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so ↵Craig Topper
they get instantiated together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172704 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17Provide a place for targets to insert ILP optimization passes.Jakob Stoklund Olesen
Move the early if-conversion pass into this group. ILP optimizations usually need to find the right balance between register pressure and ILP using the MachineTraceMetrics analysis to identify critical paths and estimate other costs. Such passes should run together so they can share dominator tree and loop info analyses. Besides if-conversion, future passes to run here here could include expression height reduction and ARM's MLxExpansion pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-16Change CostTable model to be global to all targetsRenato Golin
Moving the X86CostTable to a common place, so that other back-ends can share the code. Also simplifying it a bit and commoning up tables with one and two types on operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172658 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14[ms-inline asm] Extend support for parsing Intel bracketed memory operands thatChad Rosier
have an arbitrary ordering of the base register, index register and displacement. rdar://12527141 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Simplify nested strconcats in X86 td files since strconcat can take more ↵Craig Topper
than 2 arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172379 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents ↵Craig Topper
needing to specify everything twice. No functional change intended git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172378 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13Fix typo in comment.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-13X86: Add patterns for X86ISD::VSEXT in registers.Benjamin Kramer
Those can occur when something between the sextload and the store is on the same chain and blocks isel. Fixes PR14887. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11Update patch for the pad short functions pass for Intel Atom (only).Preston Gurd
Adds a check for -Oz, changes the code to not re-visit BBs, and skips over DBG_VALUE instrs. Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11X86AsmParser.cpp: Fix up r172148, to add initializer in another CreateMem().NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10Remove heavy and unused #inclues from X86TargetObjectFile.cpp.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10[ms-inline asm] Make sure we set a default value for AddressOf. Follow on toChad Rosier
r172121. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10[ms-inline asm] Add support for calling functions from inline assembly.Chad Rosier
Part of rdar://12991541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09ARM Cost model: Use the size of vector registers and widest vectorizable ↵Nadav Rotem
instruction to determine the max vectorization factor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172010 91177308-0d34-0410-b5e6-96231b3b80d8
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