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2011-10-13Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper
processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11Add X86 LZCNT instruction. Including instruction selection support.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09Add Ivy Bridge 16-bit floating point conversion instructions for the X86 ↵Craig Topper
disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03Add support for MOVBE and RDRAND instructions for the assembler and ↵Craig Topper
disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-05Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certainNick Lewycky
instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, ↵NAKAMURA Takumi
to appease test/CodeGen/X86 on cygwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135564 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Restore old behavior. Always auto-detect features unless cpu or features are ↵Evan Cheng
specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134757 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07Add Mode64Bit feature and sink it down to MC layer.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01- Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng
itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng
be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-23Remove TargetOptions.h dependency from X86Subtarget.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar
predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Target/X86: Eliminate uses of getDarwinVers().Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Target/X86: Add getTargetTriple() accessor.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22Stack alignment is 16 bytes on FreeBSD/i386 too.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-21The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi
No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-17Fix whitespace.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-01Patches to build EFI with Clang/LLVM. By Carl Norum.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124639 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10Formalize the notion that AVX and SSE are non-overlapping extensions from ↵Nate Begeman
the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-04Add patterns for the x86 popcnt instruction.Benjamin Kramer
- Also adds a new POPCNT subtarget feature that is currently enabled if the target supports SSE4.2 (nehalem) or SSE4A (barcelona). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03Jim Asked us to move DataLayout on ARM back to the most specialized classes. DoRafael Espindola
so and also change X86 for consistency. Investigating if this can be improved a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18X86Subtarget.h: Fix Cygwin's TD.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114297 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Properly emit __chkstk call instead of __alloca on non-mingw windows targets.Anton Korobeynikov
Patch by Cameron Esfahani! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23Add x86 CLMUL (Carry-less multiplication) cpu featureBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-05Have the X86 backend use Triple instead of a string and some enums.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27FastISel doesn't yet handle callee-pop functions.Dan Gohman
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28Enable i16 to i32 promotion by default.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02Separate out the AES-NI instructions from the SSE4.2 instructions. AddEric Christopher
a new subtarget option for AES and check for the support. Add "westmere" line of processors and add AES-NI support to the core i7. Add a couple of TODOs for information I couldn't verify. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01Nehalem unaligned memory access is fast.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100089 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18Turning off post-ra scheduling for x86. It isn't a consistent win.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14add support for pentium class CPUs which do not have cmov,Chris Lattner
PR4841. Patch by Craig Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-2880-col violations/trailing whitespace.Mikhail Glushenkov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12Setup correct data layout to match gcc's expectations on mingw32.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-12Fix typo.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-12Tweak commit 91745, which changed target data for both Mingw and Cygwin,Duncan Sands
to not touch Cygwin: the change caused llvm-gcc build failures due to long double getting the wrong size. Patch by Aaron Gray. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-11Implement a feature (-vector-unaligned-mem) to allow targets toDavid Greene
ignore alignment requirements for SIMD memory operands. This is useful on architectures like the AMD 10h that do not trap on unaligned references if a status bit is twiddled at startup time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93151 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-22Remove target attribute break-sse-dep. Instead, do not fold load into sse ↵Evan Cheng
partial update instructions unless optimizing for size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-19Bump alignment requirements for windows targets to achieve compartibility ↵Anton Korobeynikov
with vcpp. Based on patch by Michael Beck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91745 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18On recent Intel u-arch's, folding loads into some unary SSE instructions canEvan Cheng
be non-optimal. To be precise, we should avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g. movss (%rdi), %xmm0 cvtss2sd %xmm0, %xmm0 instead of cvtss2sd (%rdi), %xmm0 An alternative method to break dependency is to clear the register first. e.g. xorps %xmm0, %xmm0 cvtss2sd (%rdi), %xmm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-20Target-independent support for TargetFlags on BlockAddress operands,Dan Gohman
and support for blockaddresses in x86-32 PIC mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13Allow target to specify regclass for which antideps will only be broken ↵David Goodwin
along the critical path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10Fixed to address code review. No functional changes.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10Allow targets to specify register classes whose member registers should not ↵David Goodwin
be renamed to break anti-dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07indicate what the native integer types for the target are.Chris Lattner
Please verify. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86397 91177308-0d34-0410-b5e6-96231b3b80d8
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