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2008-12-18Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1.Mon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61211 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86'sDan Gohman
foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60461 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions ↵Evan Cheng
except they do not have any operands. The RegModRM byte is encoded with register number 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57692 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-16Fix the predicate for memop64 to be a regular load, not justDan Gohman
an unindexed load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57612 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-15Now that predicates can be composed, simplify several ofDan Gohman
the predicates by extending simple predicates to create more complex predicates instead of duplicating the logic for the simple predicates. This doesn't reduce much redundancy in DAGISelEmitter.cpp's generated source yet; that will require improvements to DAGISelEmitter.cpp's instruction sorting, to make it more effectively group nodes with similar predicates together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57565 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-10Fix SSE4.1 roundss, roundsd. While the instructions have Dale Johannesen
the same pattern as roundpd/roundps, the Intel compiler builtins do not: rounds* has an extra operand. Fixes gcc.target/i386/sse4_1-rounds[sd]-[1234].c git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57370 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-07Certain patterns involving the "movss" instruction were marked as requiring ↵Anders Carlsson
SSE2, when in reality movss is an SSE1 instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57246 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-02"The original bug was a complaint that _mm_srli_si128 mis-compiled when passedBill Wendling
a constant vector ("{0x123, 0x456}" syntax). The fix is to simplify the _mm_srli_si128 macro, and move the "* 8" from the macro into the compiler back-end. I can't change the existing __builtins because so many people are using them :-(." Patch by Stuart Hastings! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56944 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-26Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless ↵Evan Cheng
optimizing for code size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56711 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-26unpckhps requires sse1, punpckhdq requires sse2.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56697 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-25With sse3 and when the source is a load or has multiple uses, favors movddup ↵Evan Cheng
over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56620 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-25pmovsxbq etc. requires sse4.1.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56600 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24Fix patterns for SSE4.1 move and sign extend instructions. Also add ↵Evan Cheng
instructions which fold VZEXT_MOVL and VZEXT_LOAD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56594 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-12Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman
with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x Eli Friedman
i32>. This is a little messy, but it works. We should really get rid of the intrinsics, though, since they map perfectly well to standard LLVM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55864 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-28FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55466 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20Tablegen generated code already tests the opcode value, so it's notDan Gohman
necessary to use dyn_cast in these predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55055 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-08Add an EXTRACTPSmr pattern to match the pattern thatDan Gohman
X86ISelLowering creates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54544 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-05Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54376 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-17Fix a typo in last commitNate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53720 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-17SSE codegen for vsetcc nodesNate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53719 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-10Fix for PR2472. Use movss to set lower 32-bits of a zero XMM vector.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53386 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16Horizontal-add instructions are not commutative.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52363 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16mpsadbw is commutable.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52352 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-13Disable some DAG combiner optimizations that may beDuncan Sands
wrong for volatile loads and stores. In fact this is almost all of them! There are three types of problems: (1) it is wrong to change the width of a volatile memory access. These may be used to do memory mapped i/o, in which case a load can have an effect even if the result is not used. Consider loading an i32 but only using the lower 8 bits. It is wrong to change this into a load of an i8, because you are no longer tickling the other three bytes. It is also unwise to make a load/store wider. For example, changing an i16 load into an i32 load is wrong no matter how aligned things are, since the fact of loading an additional 2 bytes can have i/o side-effects. (2) it is wrong to change the number of volatile load/stores: they may be counted by the hardware. (3) it is wrong to change a volatile load/store that requires one memory access into one that requires several. For example on x86-32, you can store a double in one processor operation, but to store an i64 requires two (two i32 stores). In a multi-threaded program you may want to bitcast an i64 to a double and store as a double because that will occur atomically, and be indivisible to other threads. So it would be wrong to convert the store-of-double into a store of an i64, because this will become two i32 stores - no longer atomic. My policy here is to say that the number of processor operations for an illegal operation is undefined. So it is alright to change a store of an i64 (requires at least two stores; but could be validly lowered to memcpy for example) into a store of double (one processor op). In short, if the new store is legal and has the same size then I say that the transform is ok. It would also be possible to say that transforms are always ok if before they were illegal, whether after they are illegal or not, but that's more awkward to do and I doubt it buys us anything much. However this exposed an interesting thing - on x86-32 a store of i64 is considered legal! That is because operations are marked legal by default, regardless of whether the type is legal or not. In some ways this is clever: before type legalization this means that operations on illegal types are considered legal; after type legalization there are no illegal types so now operations are only legal if they really are. But I consider this to be too cunning for mere mortals. Better to do things explicitly by testing AfterLegalize. So I have changed things so that operations with illegal types are considered illegal - indeed they can never map to a machine operation. However this means that the DAG combiner is more conservative because before it was "accidentally" performing transforms where the type was illegal because the operation was nonetheless marked legal. So in a few such places I added a check on AfterLegalize, which I suppose was actually just forgotten before. This causes the DAG combiner to do slightly more than it used to, which resulted in the X86 backend blowing up because it got a slightly surprising node it wasn't expecting, so I tweaked it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52254 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51667 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28Fix the encoding for two more "rm" instructions that were using MRMSrcReg.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51630 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28Fixed X86 encoding error CVTPS2PD and CVTPD2PS when the source operandMon P Wang
is a memory location git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51626 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24Eliminate x86.sse2.punpckh.qdq and x86.sse2.punpckl.qdq.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51533 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24Eliminate x86.sse2.movs.d, x86.sse2.shuf.pd, x86.sse2.unpckh.pd, and ↵Evan Cheng
x86.sse2.unpckl.pd intrinsics. These will be lowered into shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51531 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-24Remove x86.sse2.loadh.pd and x86.sse2.loadl.pd. These will be lowered into ↵Evan Cheng
load and shuffle instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51522 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23Use movlps / movhps to modify low / high half of 16-byet memory location.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51501 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23Fix a duplicated pattern.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51490 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And addDan Gohman
load-folding table entries for PMULDQ and PMULLD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51489 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-23Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed ↵Evan Cheng
many 'ps' load folding patterns in X86InstrSSE.td which are missing the proper alignment checks. Also fixed some 80 col. violations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51462 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-22Add missing patterns.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51435 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-20movsd and movq do not require 16-byte alignment. This fixes vec_set-5.ll on ↵Evan Cheng
Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51327 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13Fix one more encoding bug.Nate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51057 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-13Fix and encoding error in the psrad xmm, imm8 instruction.Nate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51020 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12Teach Legalize how to scalarize VSETCCNate Begeman
Teach X86 a few more vsetcc patterns. Custom lowering for unsupported ones is next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51009 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12Initial X86 codegen support for VSETCC.Nate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51000 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-10Some clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50929 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09Add a pattern to do move the low element of a v4f32 and zero extend the rest.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50922 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-09Handle a few more cases of folding load i64 into xmm and zero top bits.Evan Cheng
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50918 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-08Use movq to move low half of XMM register and zero-extend the rest.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50874 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-08Handle vector move / load which zero the destination register top bits (i.e. ↵Evan Cheng
movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This ↵Evan Cheng
allow us to simplify the horribly complicated matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-0280 column violation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50575 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-20A better fix for my previous patch, MOVZQI2PQIrr just requires SSE2.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49986 91177308-0d34-0410-b5e6-96231b3b80d8
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