| Age | Commit message (Expand) | Author |
|---|
| 2008-12-18 | Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1. | Mon P Wang |
| 2008-12-03 | Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. | Dan Gohman |
| 2008-12-03 | Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86's | Dan Gohman |
| 2008-10-17 | Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions ... | Evan Cheng |
| 2008-10-16 | Fix the predicate for memop64 to be a regular load, not just | Dan Gohman |
| 2008-10-15 | Now that predicates can be composed, simplify several of | Dan Gohman |
| 2008-10-10 | Fix SSE4.1 roundss, roundsd. While the instructions have | Dale Johannesen |
| 2008-10-07 | Certain patterns involving the "movss" instruction were marked as requiring S... | Anders Carlsson |
| 2008-10-02 | "The original bug was a complaint that _mm_srli_si128 mis-compiled when passed | Bill Wendling |
| 2008-09-26 | Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless op... | Evan Cheng |
| 2008-09-26 | unpckhps requires sse1, punpckhdq requires sse2. | Evan Cheng |
| 2008-09-25 | With sse3 and when the source is a load or has multiple uses, favors movddup ... | Evan Cheng |
| 2008-09-25 | pmovsxbq etc. requires sse4.1. | Evan Cheng |
| 2008-09-24 | Fix patterns for SSE4.1 move and sign extend instructions. Also add instructi... | Evan Cheng |
| 2008-09-12 | Rename ConstantSDNode::getValue to getZExtValue, for consistency | Dan Gohman |
| 2008-09-05 | Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x | Eli Friedman |
| 2008-08-28 | FsFLD0S{S|D} and V_SETALLONES are as cheap as moves. | Evan Cheng |
| 2008-08-20 | Tablegen generated code already tests the opcode value, so it's not | Dan Gohman |
| 2008-08-08 | Add an EXTRACTPSmr pattern to match the pattern that | Dan Gohman |
| 2008-08-05 | Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64. | Evan Cheng |
| 2008-07-17 | Fix a typo in last commit | Nate Begeman |
| 2008-07-17 | SSE codegen for vsetcc nodes | Nate Begeman |
| 2008-07-10 | Fix for PR2472. Use movss to set lower 32-bits of a zero XMM vector. | Evan Cheng |
| 2008-06-16 | Horizontal-add instructions are not commutative. | Evan Cheng |
| 2008-06-16 | mpsadbw is commutable. | Evan Cheng |
| 2008-06-13 | Disable some DAG combiner optimizations that may be | Duncan Sands |
| 2008-05-29 | Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. | Evan Cheng |
| 2008-05-28 | Fix the encoding for two more "rm" instructions that were using MRMSrcReg. | Dan Gohman |
| 2008-05-28 | Fixed X86 encoding error CVTPS2PD and CVTPD2PS when the source operand | Mon P Wang |
| 2008-05-24 | Eliminate x86.sse2.punpckh.qdq and x86.sse2.punpckl.qdq. | Evan Cheng |
| 2008-05-24 | Eliminate x86.sse2.movs.d, x86.sse2.shuf.pd, x86.sse2.unpckh.pd, and x86.sse2... | Evan Cheng |
| 2008-05-24 | Remove x86.sse2.loadh.pd and x86.sse2.loadl.pd. These will be lowered into lo... | Evan Cheng |
| 2008-05-23 | Use movlps / movhps to modify low / high half of 16-byet memory location. | Evan Cheng |
| 2008-05-23 | Fix a duplicated pattern. | Evan Cheng |
| 2008-05-23 | Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add | Dan Gohman |
| 2008-05-23 | Bug: rcpps can only folds a load if the address is 16-byte aligned. Fixed man... | Evan Cheng |
| 2008-05-22 | Add missing patterns. | Evan Cheng |
| 2008-05-20 | movsd and movq do not require 16-byte alignment. This fixes vec_set-5.ll on L... | Evan Cheng |
| 2008-05-13 | Fix one more encoding bug. | Nate Begeman |
| 2008-05-13 | Fix and encoding error in the psrad xmm, imm8 instruction. | Nate Begeman |
| 2008-05-12 | Teach Legalize how to scalarize VSETCC | Nate Begeman |
| 2008-05-12 | Initial X86 codegen support for VSETCC. | Nate Begeman |
| 2008-05-10 | Some clean up. | Evan Cheng |
| 2008-05-09 | Add a pattern to do move the low element of a v4f32 and zero extend the rest. | Evan Cheng |
| 2008-05-09 | Handle a few more cases of folding load i64 into xmm and zero top bits. | Evan Cheng |
| 2008-05-08 | Use movq to move low half of XMM register and zero-extend the rest. | Evan Cheng |
| 2008-05-08 | Handle vector move / load which zero the destination register top bits (i.e. ... | Evan Cheng |
| 2008-05-03 | Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This ... | Evan Cheng |
| 2008-05-02 | 80 column violation. | Evan Cheng |
| 2008-04-20 | A better fix for my previous patch, MOVZQI2PQIrr just requires SSE2. | Chris Lattner |
