| Age | Commit message (Expand) | Author |
|---|
| 2009-06-06 | Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL | Eli Friedman |
| 2009-06-06 | Get rid of a bogus pattern that interferes with optimization. | Eli Friedman |
| 2009-06-03 | Evan says it's wrong; back out 72808. | Stuart Hastings |
| 2009-06-03 | Recognize another euphemism for MOVDQ2Q. | Stuart Hastings |
| 2009-05-28 | "The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but | Bill Wendling |
| 2009-04-27 | 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan. | Nate Begeman |
| 2009-04-24 | Revert 69952. Causes testsuite failures on linux x86-64. | Rafael Espindola |
| 2009-04-24 | PR2957 | Nate Begeman |
| 2009-02-23 | Only v1i16 (i.e. _m64) is returned via RAX / RDX. | Evan Cheng |
| 2008-12-12 | Added support for SELECT v8i8 v4i16 for X86 (MMX) | Mon P Wang |
| 2008-12-03 | Use mmx (punpckldq VR64, (mmx_v_set0)) to clear high 32-bits of a VR64 register. | Evan Cheng |
| 2008-12-03 | Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. | Dan Gohman |
| 2008-11-05 | Add more vector move low and zero-extend patterns. | Evan Cheng |
| 2008-08-27 | Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the | Bill Wendling |
| 2008-08-25 | Nevermind. This broke the bootstrap (?!). | Bill Wendling |
| 2008-08-25 | MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these | Bill Wendling |
| 2008-08-23 | Provide a 64 bit variant of mmx.maskmovq intrinsic lowering. | Anton Korobeynikov |
| 2008-07-25 | Remove dead PatLeaf; there are a number of issues around MMX movl that need t... | Nate Begeman |
| 2008-06-24 | Add v2f32 (MMX) type to X86. Support is primitive: | Dale Johannesen |
| 2008-05-29 | Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. | Evan Cheng |
| 2008-05-09 | Handle a few more cases of folding load i64 into xmm and zero top bits. | Evan Cheng |
| 2008-05-08 | Handle vector move / load which zero the destination register top bits (i.e. ... | Evan Cheng |
| 2008-05-03 | Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This ... | Evan Cheng |
| 2008-04-25 | Fix illegal MMX_MOVDQ2Qrr pattern. vector_extract result must be a scalar value. | Evan Cheng |
| 2008-04-25 | Special handling for MMX values being passed in either GPR64 or lower 64-bits... | Evan Cheng |
| 2008-04-25 | Fix MMX_MOVQ2DQrr pattern. It's illegal to do a bitconvert from a smaller typ... | Evan Cheng |
| 2008-04-21 | Fix the encoding of the MMX movd that moves from MMX to 64-bit GPR. | Dan Gohman |
| 2008-04-15 | Add movd instructions to move from MMX registers | Dan Gohman |
| 2008-03-21 | Undo 48570. Correctly match mmx shift instructions with an immediate operand. | Evan Cheng |
| 2008-03-19 | Add intrinsics to match mmx shift builtin's with immediate operand. | Evan Cheng |
| 2008-03-15 | Replace all target specific implicit def instructions with a target independe... | Evan Cheng |
| 2008-03-12 | Clean up my own mess. | Evan Cheng |
| 2008-02-29 | Use the correct instruction encodings for the 64-bit MMX movd. | Anders Carlsson |
| 2008-02-18 | - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should c... | Evan Cheng |
| 2008-01-10 | Start inferring side effect information more aggressively, and fix many bugs ... | Chris Lattner |
| 2008-01-10 | remove explicit sets of 'neverHasSideEffects' that can now be | Chris Lattner |
| 2008-01-06 | rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. | Chris Lattner |
| 2007-12-29 | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner |
| 2007-12-17 | Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I | Bill Wendling |
| 2007-12-12 | Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materia... | Evan Cheng |
| 2007-11-25 | Fix a long standing deficiency in the X86 backend: we would | Chris Lattner |
| 2007-09-11 | Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. | Evan Cheng |
| 2007-08-30 | Mark load instructions with isLoad = 1. | Evan Cheng |
| 2007-08-02 | Mark the SSE and MMX load instructions that | Dan Gohman |
| 2007-07-31 | Change the x86 assembly output to use tab characters to separate the | Dan Gohman |
| 2007-07-31 | Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v... | Evan Cheng |
| 2007-07-19 | Change instruction description to split OperandList into OutOperandList and | Evan Cheng |
| 2007-07-04 | Support generation of GR64 to MMX code in the JIT. | Bill Wendling |
| 2007-07-04 | Allow a GR64 to be moved into an MMX register via the "movd" instruction. | Bill Wendling |
| 2007-06-26 | Revert the earlier change that removed the M_REMATERIALIZABLE machine | Dan Gohman |
