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2009-07-10some minor simplifications.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75274 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10CMOVxx doesn't swap operands which it's commuted.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75266 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10change isGlobalStubReference to take target flags instead of a MachineOperand.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75236 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10convert some late code (called by regalloc and code emission)Chris Lattner
to use isGlobalStubReference instead of GVRequiresExtraLoad (which should really be part of isel). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75234 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10GVRequiresExtraLoad is now never used for calls, simplify it based on this.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75232 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09Targets sometimes assign fixed stack object to spill certain callee-savedEvan Cheng
registers based on dynamic conditions. For example, X86 EBP/RBP, when used as frame register has to be spilled in the first fixed object. It should inform PEI this so it doesn't get allocated another stack object. Also, it should not be spilled as other callee-saved registers but rather its spilling and restoring are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75116 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-09simplify some code based on the fact that picstyles != none are only valid Chris Lattner
in pic or dynamic-no-pic mode. Also, x86-64 never used picstylegot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75101 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08Start converting to new error handling API.Torok Edwin
cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-30Add a bit IsUndef to MachineOperand. This indicates the def / use register ↵Evan Cheng
operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27factor some logic out into a helper function, allow remat of loads from constantChris Lattner
globals. This implements remat-constant.ll even without aggressive-remat. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74373 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27Reimplement rip-relative addressing in the X86-64 backend. The newChris Lattner
implementation primarily differs from the former in that the asmprinter doesn't make a zillion decisions about whether or not something will be RIP relative or not. Instead, those decisions are made by isel lowering and propagated through to the asm printer. To achieve this, we: 1. Represent RIP relative addresses by setting the base of the X86 addr mode to X86::RIP. 2. When ISel Lowering decides that it is safe to use RIP, it lowers to X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to X86ISD::Wrapper as before. 3. This removes isRIPRel from X86ISelAddressMode, representing it with a basereg of RIP instead. 4. The addressing mode matching logic in isel is greatly simplified. 5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate passed through various printoperand routines is gone now. 6. The various symbol printing routines in asmprinter now no longer infer when to emit (%rip), they just print the symbol. I think this is a big improvement over the previous situation. It does have two small caveats though: 1. I implemented a horrible "no-rip" modifier for the inline asm "P" constraint modifier. This is a short term hack, there is a much better, but more involved, solution. 2. I had to xfail an -aggressive-remat testcase because it isn't handling the use of RIP in the constant-pool reading instruction. This specific test is easy to fix without -aggressive-remat, which I intend to do next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25Use target-specific machine operand flags to eliminate a gross hackChris Lattner
from the asmprinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74184 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-25just eliminate the code entirely!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74183 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,Eli Friedman
the code tried to use "push", which doesn't exist for XMM registers.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72836 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28The MONITOR and MWAIT instructions have insufficient information forBill Wendling
decoding. Essentially, they both map to the same column in the "opcode extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm complicates decoding this. Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code emitter special case these, a la [SML]FENCE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72556 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling
booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12Avoid unneeded SIB byte encoding. Patch by Zoltan Varga.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71520 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-08Optimize code placement in loop to eliminate unconditional branches or move ↵Evan Cheng
unconditional branch to the outside of the loop. e.g. /// A: /// ... /// <fallthrough to B> /// /// B: --> loop header /// ... /// jcc <cond> C, [exit] /// /// C: /// ... /// jmp B /// /// ==> /// /// A: /// ... /// jmp B /// /// C: --> new loop header /// ... /// <fallthough to B> /// /// B: /// ... /// jcc <cond> C, [exit] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71209 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-05Revert part of 70929 that has to do with determining whether a SIB byte is ↵Evan Cheng
needed. It causes a lot of x86_64 JIT failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-04- Avoid the longer SIB encoding on x86_64 when it's not needed.Evan Cheng
- Synchronize instruction length computation code in X86InstrInfo with code in X86CodeEmitter.cpp Patch by Zoltan Varga. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70929 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use theseDan Gohman
to precisely describe the h-register subreg register classes. Thanks to Jakob Stoklund Olesen for spotting this and for the initial patch! Also, make getStoreRegOpcode and getLoadRegOpcode aware of the needs of h registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70211 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,Dan Gohman
GR32_ABCD, and GR64_ABCD, respectively, to help describe them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-20Make X86's copyRegToReg able to handle copies to and from subclasses.Dan Gohman
This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp unnecessary. Derived from a patch by Jakob Stoklund Olesen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69635 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18Fixed a few 64 bit cases in X86InstrInfo::commuteInstructionMon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69417 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17Recommit r69335 and r69336. These were not causing problems.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69394 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17Revert r69335 and r69336. They were causing build failures.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69347 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17MOV8rr_NOREX is a "Move" instruction. This doesn't currentlyDan Gohman
matter, because this instruction isn't generated until after things that care. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69336 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything atDan Gohman
present, but it's inconsistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69335 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15Fix 80-column violations.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69204 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15Add a folding table entry for MOV8rr_NOREX.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69203 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it whenDan Gohman
either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69111 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Implement x86 h-register extract support.Dan Gohman
- Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Fix another hard-coded constant to use X86AddrNumOperands.Dan Gohman
This unbreaks the JIT on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09Fix code size computation on x86-64, patch by Zoltan Varga!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68690 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Re-apply 68552.Rafael Espindola
Tested by bootstrapping llvm-gcc and using that to build llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07Temporarily revert r68552. This was causing a failure in the self-hosting LLVMBill Wendling
builds. --- Reverse-merging (from foreign repository) r68552 into '.': U test/CodeGen/X86/tls8.ll U test/CodeGen/X86/tls10.ll U test/CodeGen/X86/tls2.ll U test/CodeGen/X86/tls6.ll U lib/Target/X86/X86Instr64bit.td U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86CodeEmitter.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86InstrInfo.h U lib/Target/X86/X86ISelDAGToDAG.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86ISelLowering.h U lib/Target/X86/X86InstrInfo.cpp U lib/Target/X86/X86InstrBuilder.h U lib/Target/X86/X86RegisterInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07Reduce code duplication on the TLS implementation.Rafael Espindola
This introduces a small regression on the generated code quality in the case we are just computing addresses, not loading values. Will work on it and on X86-64 support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28Have only one definition of X86AddrNumOperands.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67949 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-28Make code a bit less brittle by no hardcoding the numberRafael Espindola
of operands in an address in so many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67945 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-27Avoid hardcoding that X86 addresses have 4 operands.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67848 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-13Fix some significant problems with constant pools that resulted in ↵Evan Cheng
unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04Correct this comment.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66057 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04When using MachineInstr operand indices on SDNodes, the numberDan Gohman
of MachineInstr def operands must be subtracted out. This bug was uncovered by the recent x86 EFLAGS optimization. Before that, the only instructions that ever needed unfolding were things like CMP32rm, where NumDefs is zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66056 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22Do not consider MMX_MOVD64rr a move instructions. The source register is in ↵Evan Cheng
GR32, the destination is VR64. They are not compatible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18Factor out the code to add a MachineOperand to a MachineInstrBuilder.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13Remove non-DebugLoc versions of BuildMI from X86.Dale Johannesen
There were some that might even matter in X86FastISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64437 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-12Eliminate a couple of non-DebugLoc BuildMI variants.Dale Johannesen
Modify callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-11Propagate DebugLoc info for spiller call-backs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64329 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09Implement FpSET_ST1_*.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64186 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng
suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
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