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2009-06-27Reimplement rip-relative addressing in the X86-64 backend. The newChris Lattner
implementation primarily differs from the former in that the asmprinter doesn't make a zillion decisions about whether or not something will be RIP relative or not. Instead, those decisions are made by isel lowering and propagated through to the asm printer. To achieve this, we: 1. Represent RIP relative addresses by setting the base of the X86 addr mode to X86::RIP. 2. When ISel Lowering decides that it is safe to use RIP, it lowers to X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to X86ISD::Wrapper as before. 3. This removes isRIPRel from X86ISelAddressMode, representing it with a basereg of RIP instead. 4. The addressing mode matching logic in isel is greatly simplified. 5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate passed through various printoperand routines is gone now. 6. The various symbol printing routines in asmprinter now no longer infer when to emit (%rip), they just print the symbol. I think this is a big improvement over the previous situation. It does have two small caveats though: 1. I implemented a horrible "no-rip" modifier for the inline asm "P" constraint modifier. This is a short term hack, there is a much better, but more involved, solution. 2. I had to xfail an -aggressive-remat testcase because it isn't handling the use of RIP in the constant-pool reading instruction. This specific test is easy to fix without -aggressive-remat, which I intend to do next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20change TLS_ADDR lowering to lower to a real mem operand, instead of matching asChris Lattner
a global with that gets printed with the :mem modifier. All operands to lea's should be handled with the lea32mem operand kind, and this allows the TLS stuff to do this. There are several better ways to do this, but I went for the minimal change since I can't really test this (beyond make check). This also makes the use of EBX explicit in the operand list in the 32-bit, instead of implicit in the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73834 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20eliminate the "call" operand modifier from the asm descriptions, modelingChris Lattner
it as a pcrel immediate instead. This gets pc-rel weirdness out of the main printoperand codepath. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73829 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20implement support for lowering subregs when preparing to print Chris Lattner
LEA64_32r, eliminating a bunch of modifier logic stuff on addr modes. Implement support for printing mbb labels as operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73817 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16CALL64pcrel32 immediate field is 32-bit. Patch by Abhinav Duggal.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15The Ls and Qs were mixed up. Patch by Sean.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73417 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15"The Intel instruction tables should include the 64-bit and 32-bit instructionsBill Wendling
that push immediate operands of 1, 2, and 4 bytes (extended to the native register size in each case). The assembly mnemonics are "pushl" and "pushq." One such instruction appears at the beginning of the "start" function , so this is essential for accurate disassembly when unwinding." Patch by Sean Callanan! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73407 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03Revert r72734. The Darwin assembler doesn't support the staticDan Gohman
relocation model on x86-64. Higher level logic should override the relocation model to PIC on x86_64-apple-darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02Revert 72707 and 72709, for the moment.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01Make the implicit inputs and outputs of target-independentDale Johannesen
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-31Fix a grammaro and clarify a comment.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72668 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30(i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear ↵Evan Cheng
the top 8 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72618 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-29More h-registers tricks: folding zext nodes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72558 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-05Add basic support for code generation of Chris Lattner
addrspace(257) -> FS relative on x86. Patch by Zoltan Varga! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70992 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,Dan Gohman
GR32_ABCD, and GR64_ABCD, respectively, to help describe them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-27Break up long multi-mnemonic strings into separate lines for readability.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70209 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is notRafael Espindola
very elegant, but neither is the tls specification :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69968 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-21TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them.Rafael Espindola
This fixes PR4002. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69672 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17For general dynamic TLS access we must useRafael Espindola
leaq foo@TLSGD(%rip), %rdi as part of the instruction sequence. Using a register other than %rdi and then copying it to %rdi is not valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman
it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Implement x86 h-register extract support.Dan Gohman
- Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Add a comment about MOVSX64rr8.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68950 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Re-apply 68552.Rafael Espindola
Tested by bootstrapping llvm-gcc and using that to build llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07Temporarily revert r68552. This was causing a failure in the self-hosting LLVMBill Wendling
builds. --- Reverse-merging (from foreign repository) r68552 into '.': U test/CodeGen/X86/tls8.ll U test/CodeGen/X86/tls10.ll U test/CodeGen/X86/tls2.ll U test/CodeGen/X86/tls6.ll U lib/Target/X86/X86Instr64bit.td U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86CodeEmitter.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86InstrInfo.h U lib/Target/X86/X86ISelDAGToDAG.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86ISelLowering.h U lib/Target/X86/X86InstrInfo.cpp U lib/Target/X86/X86InstrBuilder.h U lib/Target/X86/X86RegisterInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07Reduce code duplication on the TLS implementation.Rafael Espindola
This introduces a small regression on the generated code quality in the case we are just computing addresses, not loading values. Will work on it and on X86-64 support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-30When optimzing a mul by immediate into two, the resulting mul's should get a ↵Evan Cheng
x86 specific node to avoid dag combiner from hacking on them further. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68066 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-18Disable the "call to immediate" optimization on x86-64. It isChris Lattner
not safe in general because the immediate could be an arbitrary value that does not fit in a 32-bit pcrel displacement. Conservatively fall back to loading the value into a register and calling through it. We still do the optzn on X86-32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address ↵Evan Cheng
assembly. 2. Fixed JIT encoding by making the address pc-relative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-11Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and theDan Gohman
assembly text output uses an indirect call ("call *") instead of a direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66735 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-05Don't use plain INC32 and DEC32 on x86-64; it needsDan Gohman
INC64_32r and INC64_16r, because these instructions are encoded differently on x86-64. This fixes JIT regressions on x86-64 in kimwitu++ and others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66207 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04Re-apply 66008, now that the unfoldMemoryOperand bug is fixed.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66058 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04Fix PR3666: isel calls to constant addresses.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04Revert r66004 for now; it's causing a variety of test failures.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66008 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-04Teach the x86 backend to eliminate "test" instructions by using the EFLAGSDan Gohman
result from add, sub, inc, and dec instructions in simple cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66004 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-03Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DECDan Gohman
instructions. These aren't used yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65965 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-1080 col violations.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64237 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05A few more isAsCheapAsAMove.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63852 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-26Map address space 256 to gs; similar mappings could be supported for theNate Begeman
other x86 segments. address space 0 is stack/default, 1-255 are reserved for client use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62980 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-21Also favors NOT64r.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62710 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-13Disable the register+memory forms of the bt instructions for now. ThanksDan Gohman
to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62194 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-13Add bt instructions that take immediate operands.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62180 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07Add patterns to match conditional moves with loads foldedDan Gohman
into their left operand, rather than their right. Do this by commuting the operands and inverting the condition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61842 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07Define instructions for cmovo and cmovno.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61836 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-25Fix some JIT encodings.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61425 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-25BT memory operands load from their address operand.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61424 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23Add instruction patterns and encodings for the x86 bt instructions.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61400 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-19Move the patterns which have i8 immediates before the patternsDan Gohman
that have i32 immediates so that they get selected first. This currently only matters in the JIT, as assemblers will automatically use the smallest encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61250 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-12- Use patterns instead of creating completely new instruction matching patterns,Bill Wendling
which are identical to the original patterns. - Change the multiply with overflow so that we distinguish between signed and unsigned multiplication. Currently, unsigned multiplication with overflow isn't working! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60963 91177308-0d34-0410-b5e6-96231b3b80d8
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