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2003-06-04Comment out opcodes currently unused in the Sparc backend.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6597 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-04Added instruction format class 3.15 and floating-point compare instructions.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6594 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-04Avoid generating a getelementptr instruction of a functionChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6591 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03Make the write*map methods more self-contained. Document some more.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6589 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03I documented this file, in an attempt to understand it, with a view towardBrian Gaeke
rewriting it. I also vacuumed out all the commented-out code and inaccurate comments, etc. (We need to put the mapping information in a data structure so that we can pass it out to the JIT, instead of automagically converting it to .byte directives.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6574 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03Use the new -o tablegen optionChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6572 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03Constants are laid out in memory in PC-relative form.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6568 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03Added opcode conversion for conditional move of integers.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6567 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03* Convert load/store opcodes from register to immediate forms.Misha Brukman
* Stop code from wrapping to the next line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6566 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03Convert load/store opcodes from register to immediate forms, if necessary.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6565 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03Store instructions are different from other Format 3.1/3.2 instructions in thatMisha Brukman
they prefer the destination register to be last. Thus, two new classes were made for them that accomodate for having this layout of operands (F3_1rd, F3_2rd). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6564 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03Moved code to modify the opcode from 'reg' to 'imm' form to a more logical ↵Misha Brukman
place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6563 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03* Added section A.34: Move FP register on int reg condition (FMOVr)Misha Brukman
* Labeled sections that are not currently used in the Sparc backend as not requiring completion at this time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6562 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03* Removed unused classes (rd field is always mentioned last); fixed comments.Misha Brukman
* Added instruction classes which start building from rs1, then rs2, and rd. * Fixed order of operands in classes 4.1 and 4.2; added 4.6 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6561 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03* Removed unused classes: the rd field is always mentioned as the last reg.Misha Brukman
* Added new classes which start building from rs1, adding rs2, and then rd. * Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 . * Fixed comments to reflect Real Life (tm). * Removed "don't care" commented out assignments and dead classes (#if 0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6560 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-03The rd field goes after the immediate field in format 2.1 instructions.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6559 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02Remove usage of noncopyable classes to clean up doxygen output.Chris Lattner
In particular these classes are the last that link the noncopyable classes with the hash_map, vector, and list classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6552 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02Add #includeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6550 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02Added MOVR (move int reg on register condition), aka comparison with zero.Misha Brukman
None of these instructions are actually used in the Sparc backend, so no changes were required in the instruction selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6549 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructionsMisha Brukman
SparcInstrSelection.cpp: * Fixed opcodes to return correct 'i' version since the two functions are each only used in one place. * Changed name of function to have an 'i' in the name to signify that they each return an immediate form of the opcode. * Added a warning if either of the functions is ever used in a context which requires a register-version opcode. SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing SparcV9.td: added the MOV(F)cc instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6548 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02* Added casts to/from floating-point to integers.Misha Brukman
* Changed // comments to #ifdef 0 to maintain syntax highlighting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6546 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02compiled with the new SchedGraphCommonGuochun Shi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6545 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02Clean up after merging in SparcEmitter.cpp; branches and return work again.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6536 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02Merged in tools/lli/JIT/SparcEmitter.cpp, coupled with the JITResolver takenMisha Brukman
from lib/Target/X86/X86CodeEmitter.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6530 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-02Deal with %lo/%lm/%hm/%hh flags in getMachineOpValue().Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6522 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-01Make the .inc file depend on $(TBLGEN), so that changes to TableGen followedBrian Gaeke
by a re-link of TableGen will notify Make to rebuild the .inc file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6512 91177308-0d34-0410-b5e6-96231b3b80d8
2003-06-01Add map info for arguments to call (copies)Anand Shukla
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6503 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Renamed a variable.Vikram S. Adve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6472 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Minor changes.Vikram S. Adve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6470 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Added MachineCodeForInstruction object as an argument toVikram S. Adve
TmpInstruction constructors because every TmpInstruction object has to be registered with a MachineCodeForInstruction to prevent leaks. This simplifies the user's code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6469 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Changes to allow explicit physical register arguments that have beenVikram S. Adve
preallocated. While reg-to-reg dependences were already handled, this change required new code for adding edges to/from call instructions. This was part of the extensive changes to the way code generation occurs for function call arguments and return values. See log for CodeGen/PhyRegAlloc.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6467 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Several bug fixes: globals in call operands were not being pulled out;Vikram S. Adve
globals in some other places may not have been pulled out either; globals in phi operands were being put just before the phi instead of in the predecessor basic blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6466 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Extensive changes to the way code generation occurs for functionVikram S. Adve
call arguments and return values: Now all copy operations before and after a call are generated during selection instead of during register allocation. The values are copied to virtual registers (or to the stack), but in the former case these operands are marked with the correct physical registers according to the calling convention. Although this complicates scheduling and does not work well with live range analysis, it simplifies the machine-dependent part of register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6465 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Reverting previous beautification changes.Vikram S. Adve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6464 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Removed useless code -- the byte order of output code is correct as is.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6462 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31The 'rd' register is consistently mentioned last in instruction definitions.Misha Brukman
Created new classes from which instructions inherit their ordering of fields. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6461 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31* Put back into action SLL/SRL/SRA{r,i}6 instructionsMisha Brukman
* Fixed page numbers referring to the Sparc manual git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6460 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Code beautification, no functional changes.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6459 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31Enabling some of these passes causes lli to breakMisha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6457 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-31The actual order of parameters in a 2-reg-immediate assembly instructions isMisha Brukman
"rs1, imm, rd": most importantly, rd goes last. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6456 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30When converting virtual registers to immediate constants, change the opcode.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6452 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Added:Misha Brukman
* ability to save BasicBlock references to be resolved later * register remappings from the enum values to the real hardware numbers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6449 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Fixed the namespace to match SparcInternals.h; added notes on some missingMisha Brukman
sections of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6448 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30The register types need to be visible outside of the class to be useful.Misha Brukman
For one, converting register numbers based on class in the code emitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6447 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.Misha Brukman
Code beautification for the rest of the code: changed layout to match the rest of the code base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6446 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Make LLI behave just like LLC with regard to the compile passes it uses.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6444 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Made the register and immediate versions of instructions consecutive.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6439 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Because the format of the shift instructions is `shift r, shcnt, r', theMisha Brukman
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that implies that the two registers are the first two parameters to the instruction. Thus I made the instructions inherit from F3rd again, and manually added an rs1 field AFTER the shcnt field in the instruction, which maps to the appropriate place in the instruction. The other changes are just elimination of unnecessary spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6437 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.Brian Gaeke
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also, their fields were totally screwed up. This seems to fix the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6429 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 so far everything compilesGuochun Shi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6423 91177308-0d34-0410-b5e6-96231b3b80d8
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