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path: root/lib/Target/R600/SIInstructions.td
AgeCommit message (Expand)Author
2013-03-27R600/SI: add SETO/SETUO patternsChristian Konig
2013-03-27R600/SI: add cummuting of rev instructionsChristian Konig
2013-03-27R600/SI: add mulhu/mulhs patternsChristian Konig
2013-03-27R600/SI: add srl/sha patterns for SIChristian Konig
2013-03-26R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig
2013-03-26R600/SI: replace WQM intrinsicChristian Konig
2013-03-22R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsicsMichel Danzer
2013-03-18R600/SI: implement indirect adressing for SIChristian Konig
2013-03-18R600/SI: add float vector typesChristian Konig
2013-03-18R600/SI: add shl patternChristian Konig
2013-03-18R600/SI: add BUFFER_LOAD_DWORD patternChristian Konig
2013-03-18R600/SI: implement SI.load.const intrinsicChristian Konig
2013-03-18R600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodesChristian Konig
2013-03-07R600/SI: rework input interpolation v2Christian Konig
2013-03-07R600/SI: remove SGPR address space v2Christian Konig
2013-03-07R600/SI: switch types of SGPRs to v*i8Christian Konig
2013-03-01R600/SI: remove S_MOV immediate patternsChristian Konig
2013-02-26R600/SI: add some more instruction flagsChristian Konig
2013-02-26R600/SI: add post ISel folding for SI v2Christian Konig
2013-02-26R600/SI: fix VOP3b encoding v2Christian Konig
2013-02-26R600/SI: fix and cleanup SI register definition v2Christian Konig
2013-02-22R600/SI: Add pattern for sign extension of i1 to i32.Michel Danzer
2013-02-22R600/SI: Add pattern for logical or of i1 values.Michel Danzer
2013-02-22R600/SI: Add pattern for fceil.Michel Danzer
2013-02-21R600/SI: inline V_ADD|SUB_F32 patternsChristian Konig
2013-02-21R600/SI: replace IMPLICIT_DEF with SIOperand.ZEROChristian Konig
2013-02-21R600/SI: replace SI_V_CNDLT with a patternChristian Konig
2013-02-21R600/SI: use patterns for clamp, fabs, fnegChristian Konig
2013-02-21R600/SI: add all the other missing asm operands v2Christian Konig
2013-02-21R600/SI: simplify VOPC_* pattern v2Christian Konig
2013-02-21R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32Michel Danzer
2013-02-18R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune
2013-02-16R600/SI: Add pattern to simplify i64 loadingChristian Konig
2013-02-16R600/SI: nuke SReg_1 v3Christian Konig
2013-02-16R600/SI: cleanup literal handling v3Christian Konig
2013-02-16R600/SI: replace AllReg_* with [SV]Src_* v2Christian Konig
2013-02-14R600/SI: Fix int_SI_fs_interp_constantMichel Danzer
2013-02-07R600/SI: Add pattern for mul.Tom Stellard
2013-02-07R600/SI: simplify and fix SMRD encodingTom Stellard
2013-02-07R600/SI: add proper 64bit immediate support v2Tom Stellard
2013-02-07R600/SI: Use proper instructions for array/shadow samplers.Tom Stellard
2013-02-07R600/SI: Make sample intrinsic address parameter type overloaded.Tom Stellard
2013-02-07R600/SI: Add basic support for more integer vector types.Tom Stellard
2013-02-07R600/SI: Add pattern for flog2Michel Danzer
2013-02-07R600: Consolidate sub register indices.Tom Stellard
2013-02-05R600/SI: Add patterns for fcos and fsin.Tom Stellard
2013-01-21R600/SI: Use unnormalized coordinates for sampling with the RECT target.Tom Stellard
2013-01-21R600/SI: Take target parameter for sample intrinsics.Tom Stellard
2013-01-18R600: Optimize and cleanup KILL on SITom Stellard
2012-12-19R600: New control flow for SI v2Tom Stellard
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