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2012-09-16Change unsigned to uint32_t to match base class declaration and other targets.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Fix PR11985Michael Liao
- BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12Enable exceptions handling on PPC64 now that cr misaligned spillingRoman Divacky
was fixed in r163713. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163715 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12This patch corrects logic in PPCFrameLowering for save and restore of ↵Roman Divacky
nonvolatile condition register fields across calls under the SVR4 ABIs. * With the 64-bit ABI, the save location is at a fixed offset of 8 from the stack pointer. The frame pointer cannot be used to access this portion of the stack frame since the distance from the frame pointer may change with alloca calls. * With the 32-bit ABI, the save location is just below the general register save area, and is accessed via the frame pointer like the rest of the save areas. This is an optional slot, so it must only be created if any of CR2, CR3, and CR4 were modified. * For both ABIs, save/restore logic is generated only if one of the nonvolatile CR fields were modified. I also took this opportunity to clean up an extra FIXME in PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless for the 64-bit ABI, so I removed them for correctness and efficiency. Fixes PR13708 and partially also PR13623. It lets us enable exception handling on PPC64. Patch by William J. Schmidt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163713 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07MC: Overhaul handling of .lcommBenjamin Kramer
- Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05Move the PPC TOC defs into the PPC64 InstrInfo file.Hal Finkel
Since TOC is just defined for PPC64, move its definition to PPC64 td file. Patch by Adhemerval Zanella. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03Remove always true checks. Noticed by Adhemerval Zanella.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30PPCISelLowering.cpp: Fix r162725.NAKAMURA Takumi
[Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good! Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30PPCISelLowering.cpp: Whitespace.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29Reserve space for the mandatory traceback fields on PPC64.Hal Finkel
We need to reserve space for the mandatory traceback fields, though leaving them as zero is appropriate for now. Although the ABI calls for these fields to be filled in fully, no compiler on Linux currently does this, and GDB does not read these fields. GDB uses the first word of zeroes during exception handling to find the end of the function and the size field, allowing it to compute the beginning of the function. DWARF information is used for everything else. We need the extra 8 bytes of pad so the size field is found in the right place. As a comparison, GCC fills in a few of the fields -- language, number of saved registers -- but ignores the rest. IBM's proprietary OSes do make use of the full traceback table facility. Patch by Bill Schmidt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Emit word of zeroes after the last instruction as a start of the mandatoryRoman Divacky
traceback table on PowerPC64. This helps gdb handle exceptions. The other mandatory fields are ignored by gdb and harder to implement so just add there a FIXME. Patch by Bill Schmidt. PR13641. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Split several PPC instruction classes.Hal Finkel
Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Allow remat of LI on PPC.Hal Finkel
Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Eliminate redundant CR moves on PPC32.Hal Finkel
The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Optimize zext on PPC64.Hal Finkel
The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith
Reviewed offline by chandlerc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky
In collaboration with Adhemerval Zanella. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162562 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Add missing SDNPSideEffect flags.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16Revert r162034, r162035 and r162037.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16Define and handle additional fixup kinds. By Adhemerval Zanella.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162037 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16Fix typo and grammar. By Adhemerval Zanella.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08Don't use getNextOperandForReg().Jakob Stoklund Olesen
This way of using getNextOperandForReg() was unlikely to work as intended. We don't give any guarantees about the order of operands in the use-def chains, so looking only at operands following a given operand in the chain doesn't make sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-07Add a comment about mftb vs. mfspr on PPC.Hal Finkel
Thanks to Alex Rosenberg for the suggestion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06MFTB on PPC64 should really be encoded using MFSPR.Hal Finkel
The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04Add readcyclecounter lowering on PPC64.Hal Finkel
On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03allow 'make CPPFLAGS=<something>' work againGabor Greif
this makes this hack a bit more bearable for poor souls who need to pass custom preprocessor flags to the build process git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161240 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen
Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Target option DisableJumpTables is a gross hack. Move it to TargetLowering ↵Evan Cheng
instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson
This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-28Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-26There are a number of generic inline asm operand modifiers thatJack Carter
up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-24llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159112 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-23Silence an unused variable warning on release builds.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Add support for the PPC isel instruction.Hal Finkel
The isel (integer select) instruction is supported on the 440 and A2 embedded cores and on the POWER7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-22Convert the PPC backend to use the new FMA infrastructure.Hal Finkel
The existing contraction patterns are replaced with fma/fneg. Overall functionality should be the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-21Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc ↵Hal Finkel
stores on PPC. Thanks to Tobias von Koch for pointing out this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158932 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-20Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add DAG-combines for aggressive FMA formation.Lang Hames
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Implement PPCInstrInfo::isCoalescableExtInstr().Jakob Stoklund Olesen
The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Mark most PPC register classes to avoid write-after-write.Hal Finkel
For processors with the G5-like instruction-grouping scheme, this helps avoid early group termination due to a write-after-write dependency within the group. It should also help on pipelined embedded cores. On POWER7, over the test suite, this gives an average 0.5% speedup. The largest speedups are: SingleSource/Benchmarks/Stanford/Quicksort - 33% MultiSource/Applications/d/make_dparser - 21% MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12% MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12% Largest slowdowns: SingleSource/Benchmarks/Stanford/Bubblesort - 23% MultiSource/Benchmarks/Prolangs-C++/city/city - 21% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16% MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-19Add support for generating reg+reg preinc stores on PPC.Hal Finkel
PPC will now generate STWUX and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-16Cleanup trip-count finding for PPC CTR loops (and some bug fixes).Hal Finkel
This cleans up the method used to find trip counts in order to form CTR loops on PPC. This refactoring allows the pass to find loops which have a constant trip count but also happen to end with a comparison to zero. This also adds explicit FIXMEs to mark two different classes of loops that are currently ignored. In addition, we now search through all potential induction operations instead of just the first. Also, we check the predicate code on the conditional branch and abort the transformation if the code is not EQ or NE, and we then make sure that the branch to be transformed matches the condition register defined by the comparison (multiple possible comparisons will be considered). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-13Add another missing 64-bit itinerary definition for the PPC A2 core.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158393 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12Add some missing 64-bit itinerary definitions for the PPC A2 core.Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12Split out the PPC instruction class IntSimple from IntGeneral.Hal Finkel
On the POWER7, adds and logical operations can also be handled in the load/store pipelines. We'll call these IntSimple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12Fixes for PPC host detection and features.Hal Finkel
POWER4 is a 64-bit CPU (better matched to the 970). The g3 is really the 750 (no altivec), the g4+ is the 74xx (not the 750). Patch by Andreas Tobler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12Reapply r158337, this time properly protect Darwin/PPC host CPU use with ↵Hal Finkel
__ppc__. Original commit message: Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName(). Both the new Linux functionality and the old Darwin functions have been moved. This change also allows this information to be queried directly by clang and other frontends (clang, for example, will now have real -mcpu=native support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158349 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12Revert r158337 "Move PPC host-CPU detection logic from PPCSubtarget into ↵Jakob Stoklund Olesen
sys::getHostCPUName()." This commit broke most of the PowerPC unit tests when running on Intel/Apple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158345 91177308-0d34-0410-b5e6-96231b3b80d8
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