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2013-03-07ArrayRefize some code. No functionality change.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176648 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01Fix PR10475Michael Liao
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-26Fix PR15332 (patch by Florian Zeitz).Bill Schmidt
There's no need to generate a stack frame for PPC32 SVR4 when there are no local variables assigned to the stack, i.e., when no red zone is needed. (PPC64 supports a red zone, but PPC32 does not.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-25Fix missing relocation for TLS addressing peephole optimization.Bill Schmidt
Report and fix due to Kai Nacke. Testcase update by me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176029 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-24Fix PR14364.Bill Schmidt
This removes a const_cast hack from PPCRegisterInfo::hasReservedSpillSlot(). The proper place to save the frame index for the CR spill slot is in the PPCFunctionInfo object, not the PPCRegisterInfo object. No new test cases, as this just reimplements existing function. Existing tests such as test/CodeGen/PowerPC/crsave.ll are sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175998 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky
to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21Trivial cleanupBill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175771 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21Large code model support for PowerPC.Bill Schmidt
Large code model is identical to medium code model except that the addis/addi sequence for "local" accesses is never used. All accesses use the addis/ld sequence. The coding changes are straightforward; most of the patch is taken up with creating variants of the medium model tests for large model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21Code review cleanup for r175697Bill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21PPCDAGToDAGISel::PostprocessISelDAG()Bill Schmidt
This patch implements the PPCDAGToDAGISel::PostprocessISelDAG virtual method to perform post-selection peephole optimizations on the DAG representation. One optimization is implemented here: folds to clean up complex addressing expressions for thread-local storage and medium code model. It will also be useful for large code model sequences when those are added later. I originally thought about doing this on the MI representation prior to register assignment, but it's difficult to do effective global dead code elimination at that point. DCE is trivial on the DAG representation. A typical example of a candidate code sequence in assembly: addis 3, 2, globalvar@toc@ha addi 3, 3, globalvar@toc@l lwz 5, 0(3) When the final instruction is a load or store with an immediate offset of zero, the offset from the add-immediate can replace the zero, provided the relocation information is carried along: addis 3, 2, globalvar@toc@ha lwz 5, globalvar@toc@l(3) Since the addi can in general have multiple uses, we need to only delete the instruction when the last use is removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175697 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21Relocation enablement for PPC DAG postprocessing passBill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Update TargetLowering ivars for name policy.Jim Grosbach
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly ivars should be camel-case and start with an upper-case letter. A few in TargetLowering were starting with a lower-case letter. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Additional fixes for bug 15155.Bill Schmidt
This handles the cases where the 6-bit splat element is odd, converting to a three-instruction sequence to add or subtract two splats. With this fix, the XFAIL in test/CodeGen/PowerPC/vec_constants.ll is removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175663 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Fix bug 14779 for passing anonymous aggregates [patch by Kai Nacke].Bill Schmidt
The PPC backend doesn't handle these correctly. This patch uses logic similar to that in the X86 and ARM backends to track these arguments properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175635 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Fix PR15155: lost vadd/vsplat optimization.Bill Schmidt
During lowering of a BUILD_VECTOR, we look for opportunities to use a vector splat. When the splatted value fits in 5 signed bits, a single splat does the job. When it doesn't fit in 5 bits but does fit in 6, and is an even value, we can splat on half the value and add the result to itself. This last optimization hasn't been working recently because of improved constant folding. To circumvent this, create a pseudo VADD_SPLAT that can be expanded during instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175632 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20Add missing #include.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175583 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17Make the visibility of LLVMPPCCompilationCallback work with GCC.Benjamin Kramer
GCC warns about the attribute being ignored if it occurs after void*. There seems to be some kind of incompatibility between clang and gcc here, but I can't fathom who's right. void* LLVM_LIBRARY_VISIBILITY foo(); // clang: hidden, gcc: default LLVM_LIBRARY_VISIBILITY void *bar(); // clang: hidden, gcc: hidden void LLVM_LIBRARY_VISIBILITY qux(); // clang: hidden, gcc: hidden git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Give these callbacks hidden visibility. It is better to not export them moreRafael Espindola
than we need to and some ELF linkers complain about directly accessing symbols with default visibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15Don't make assumptions about the mangling of static functions in extern "C"Rafael Espindola
blocks. We still don't have consensus if we should try to change clang or the standard, but llvm should work with compilers that implement the current standard and mangle those functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Revert r175120 and r175121. Clang is producing the expected asm names again.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Don't asume that a static function in an extern "C" block will not be mangled.Rafael Espindola
Since functions with internal linkage don't have language linkage, it is valid to overload them: extern "C" { static int foo(); static int foo(int); } So we mangle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13Add registration for PPC-specific passes to allow the IR to be dumpedKrzysztof Parzyszek
via -print-after-all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08Refine fix to bug 15041.Bill Schmidt
Thanks to help from Nadav and Hal, I have a more reasonable (and even correct!) approach. This specifically penalizes the insertelement and extractelement operations for the performance hit that will occur on PowerPC processors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174725 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07Constrain PowerPC autovectorization to fix bug 15041.Bill Schmidt
Certain vector operations don't vectorize well with the current PowerPC implementation. Element insert/extract performs poorly without VSX support because Altivec requires going through memory. SREM, UREM, and VSELECT all produce bad scalar code. There's a lot of work to do for the cost model before autovectorization will be tuned well, and this is not an attempt to address the larger problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174660 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06PPC calling convention cleanup.Bill Schmidt
Most of PPCCallingConv.td is used only by the 32-bit SVR4 ABI. Rename things to clarify this. Also delete some code that's been commented out for a long time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Move MRI liveouts to PowerPC return instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05Avoid using MRI::liveout_iterator for computing VRSAVEs.Jakob Stoklund Olesen
The liveout lists are about to be removed from MRI, this is the only place they were used after register allocation. Get the live out V registers directly from the return instructions instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04Disable a couple more vector splat optimizations on PPC.Benjamin Kramer
I didn't see those because the test case used "not grep". FileCheck the test and XFAIL it, preserving the old optimization, so this can be fixed eventually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04SelectionDAG: Teach FoldConstantArithmetic how to deal with vectors.Benjamin Kramer
This required disabling a PowerPC optimization that did the following: input: x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16> lowered to: tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8> x = ADD tmp, tmp The add now gets folded immediately and we're back at the BUILD_VECTOR we started from. I don't see a way to fix this currently so I left it disabled for now. Fix some trivially foldable X86 tests too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174325 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04PPCDarwinAsmPrinter::EmitStartOfAsmFile(): Add checking range in ↵NAKAMURA Takumi
CPUDirectives[]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174298 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-04PPCDarwinAsmPrinter::EmitStartOfAsmFile(): Add possible elements in ↵NAKAMURA Takumi
CPUDirectives[]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01Add notes about future PowerPC featuresBill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174232 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01LLVM enablement for some older PowerPC CPUsBill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31[PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier
Each target implementation was needlessly recomputing the index. Part of rdar://13076458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30PPC QPX requires a 32-byte aligned stackHal Finkel
On systems which support the QPX vector instructions, the stack must be 32-byte aligned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173993 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Initialize hasQPX in PPCSubtargetHal Finkel
This should have gone in with r173973. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30Add definitions for the PPC a2q core marked as having QPX availableHal Finkel
This is the first commit of a large series which will add support for the QPX vector instruction set to the PowerPC backend. This instruction set is used on the IBM Blue Gene/Q supercomputers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173973 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng
conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-29Add isBGQ method to PPCSubtargetHal Finkel
This function will be used in future commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173729 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Remove unused variables, silences -Wunused-variableDmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173526 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Initial implementation of PPCTargetTransformInfoHal Finkel
This provides a place to add customized operation cost information and control some other target-specific IR-level transformations. The only non-trivial logic in this checkin assigns a higher cost to unaligned loads and stores (covered by the included test case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25More cleanup of PPC register definitions.Hal Finkel
Uses the new !add TableGen operator to do more cleanup of the PPC register definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24Start cleanup of PPC register definitions using foreach loops.Hal Finkel
No functionality change intended. This captures the first two cases GPR32/64. For the others, we need an addition operator (if we have one, I've not yet found it). Based on a suggestion made by Tom Stellard in the AArch64 review! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Fix powerpc test failure - forgot to initialize stack slot size for ↵Eli Bendersky
PPCLinuxMCAsmInfo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and ↵Eli Bendersky
explicitly set this in every target that needs to change it from the default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173270 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19Sort all of the includes. Several files got checked in with mis-sortedChandler Carruth
includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172891 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17This patch fixes PR13626 by providing i128 support in the returnBill Schmidt
calling convention. 128-bit integers are now properly returned in GPR3 and GPR4 on PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172745 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-17This patch fixes the PPC calling convention to handle returns ofBill Schmidt
_Complex float and _Complex long double, by simply increasing the number of floating point registers available for return values. The test case verifies that the correct registers are loaded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09PowerPC: EH adjustmentsAdhemerval Zanella
This patch adjust the r171506 to make all DWARF enconding pc-relative for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT (since the eh_frame will not generate PIC-relative relocation) and also adds the emission of stubs created by the TTypeEncoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171979 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09These functions have default arguments of 0 for the last arg. UseEric Christopher
them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171933 91177308-0d34-0410-b5e6-96231b3b80d8
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