aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/PowerPC/PPCISelPattern.cpp
AgeCommit message (Collapse)Author
2006-01-12Goodbye PPC pattern isel. You have served us well, but it is now time forChris Lattner
you to ride off into the sunset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25236 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-22remove dead codeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24965 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-29Fixed a comment bug:Evan Cheng
createPPCPatternInstructionSelector -> createPPCISelPattern git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24510 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-16Patch to clean up function call pseudos and support the BLA instruction,Nate Begeman
which branches to an absolute address. This is required to support objc direct dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24370 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-20Move the target constant divide optimization up into the dag combiner, soNate Begeman
that the nodes can be folded with other nodes, and we can not duplicate code in every backend. Alpha will probably want this too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23835 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-18First bits of 64 bit PowerPC stuff, currently disabled. A lot of this isNate Begeman
purely mechanical. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-16More PPC32 -> PPC changes, as well as merging some classes that wereNate Begeman
redundant after the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-15remove broken SRA/rlwimi caseChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23746 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14Rename PPC32*.h to PPC*.hChris Lattner
This completes the grand PPC file renaming git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14Rename PowerPC*.h to PPC*.hChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14Rename PowerPCInstrBuilder.h -> PPC*Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23742 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-14Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitionsChris Lattner
from the .td file that correspond to it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23736 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-02another solution to the fsel issue. Instead of having 4 variants, just forceChris Lattner
the comparison to be 64-bits. This is fine because extensions from float to double are free. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-02fsel can take a different FP type for the comparison and for the result. As ↵Chris Lattner
such split the FSEL family into 4 things instead of just two. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23588 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-01Modify the ppc backend to use two register classes for FP: F8RC and F4RC.Chris Lattner
These are used to represent float and double values, and the two regclasses contain the same physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-29consistency with other cases, no functionality changeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23524 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-28Add FP versions of the binary operators, keeping the int and fp worlds seperate.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23506 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-10PowerPC cannot truncstore i1 nativelyChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23304 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-06Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when weNate Begeman
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts, such as the PowerPC 970. This speeds up 189.lucas from 81.99 to 32.64 seconds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23250 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-31Move FCTIWZ handling out of the instruction selectors and into legalization,Chris Lattner
getting them out of the business of making stack slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23180 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-31Remove dead codeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23179 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-31Remove code that is now dead from the pattern isel.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23177 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-31Handle AssertSext/AssertZext nodes, fixing the regressions last night.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23170 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26Make fsel emission work with both the pattern and dag-dag selectors, byChris Lattner
giving it a non-instruction opcode. The dag->dag selector used to not select the operands of the fsel, because it thought that whole tree was already selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23091 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26Remove some code made dead by the fsel patchNate Begeman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23085 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26now that fsel is formed during legalization, this code is deadChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23084 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26Change ConstantPoolSDNode to actually hold the Constant itself instead ofChris Lattner
putting it into the constant pool. This allows the isel machinery to create constants that it will end up deciding are not needed, without them ending up in the resultant function constant pool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23081 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26Fix some warnings in an optimized buildChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23080 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-26add initial support for converting select_cc -> fsel in the legalizerChris Lattner
instead of in the backend. This currently handles fsel cases with registers, but doesn't have the 0.0 and -0.0 optimization enabled yet. Once this is finished, special hack for fp immediates can go away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23075 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-25simplify the add/sub_parts codeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23065 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-25Simplify some code. It's not clear why the UDIV expanded sequenceChris Lattner
doesn't work for large uint constants, but we'll keep the current behavior git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23061 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-25fit in 80 colsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23051 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-24Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that theChris Lattner
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag selector to generate this, fixing UnitTests/2003-07-06-IntOverflow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23028 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-24Remove some dead cases.Chris Lattner
Emit the indcall sequence as: mtctr inreg mr R12, inreg btctr If inreg and R12 aren't coallesced, this reduces the odds of having the mtctr and btctr in the same dispatch group. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23023 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-24Whoops, fix a thinko. All cases except SETNE are now handled by theNate Begeman
target independent code in SelectionDAG.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23002 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-24Add the "ppc specific" setcc-equivalent select_cc casesNate Begeman
Prefer 'neg X' to 'subfic 0, X' since it does not set XER[CA] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23000 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-22Make sure expressions only have one use before emitting them into a place ↵Chris Lattner
that is conditionally executed git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22960 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-21Simplify the logic for BRTWOWAY_CC handling. The isel code alreadyChris Lattner
simplifies BRTWOWAY into BR if one of the results is a fall-through. Unless I'm missing something, there is no reason to duplicate this in the target-specific code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22952 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-21If the false value for a select_cc is really simple (has no inputs), evaluateChris Lattner
it in the block. This codegens: int %test(bool %c) { %retval = select bool %c, int 17, int 1 ret int %retval } as: _test: rlwinm r2, r3, 0, 31, 31 li r2, 17 cmpwi cr0, r3, 0 bne .LBB_test_2 ; .LBB_test_1: ; li r2, 1 .LBB_test_2: ; or r3, r2, r2 blr instead of: _test: rlwinm r2, r3, 0, 31, 31 li r2, 17 li r4, 1 cmpwi cr0, r3, 0 bne .LBB_test_2 ; .LBB_test_1: ; or r2, r4, r4 .LBB_test_2: ; or r3, r2, r2 blr ... which is one fewer instruction. The savings are more significant for global address and constantfp nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22946 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19Fix a bug where we were passing the wrong number of arguments to anNate Begeman
instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22901 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18MFLR doesn't take an operand, the LR register is implicitChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22882 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18More optimal solution for loading constants.Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22870 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18Fix int foo() { return 65535; } by using the top 16 bits of the constantNate Begeman
as the argument to LIS rather than the result of HA16(constant). The DAG->DAG ISel was already doing the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22865 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18Improve ISD::Constant codegen.Nate Begeman
Now for int foo() { return -1; } we generate: _foo: li r3, -1 blr instead of _foo: lis r2, -1 ori r3, r2, 65535 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22864 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18replace switch stmt with an assert, generate li 0 instead of lis 0 for 0,Chris Lattner
to make the code follow people's expectations better. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22861 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18Handle loading of 0x????0000 constants with a single instruction.Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22858 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18Better version of isIntImmediate.Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22848 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-17Fix a few small typos I noticed when converting this over to the DAG->DAGChris Lattner
selector. Also, there is no difference between addSImm and addImm, so just use addImm, folding some branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22819 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-17Removed UINT_TO_FP and SINT_TO_FP from ISel outright.Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22818 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-17Remove ISel code generation for UINT_TO_FP and SINT_TO_FP. Now asserts ifJim Laskey
marked as legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22816 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-04-28 13:58:51 +0000